tag: Mentor Graphics

The FPGA Alternative
By Various Writers - 31 Oct, 2009 - Comments: 0

By Geoffrey James Until a few years ago, SoC designers focused almost exclusively on ASICs. While it was theoretically possible to create an SoC design for an FPGA, the programmable chips were too bulky and pricey to be useful for much more than prototyping. Today, however, designers are increasingly turning to FPGAs for their SOC targets for production systems. Why the sudden upsurge in So... » read more

The Abstraction of Test
By Ann Mutschler - 29 Oct, 2009 - Comments: 0

By Ann Steffora Mutschler By now, semiconductor design abstraction is old hat to many engineers, but mention the term “semiconductor test abstraction” and expect a blank stare in return. Design complexity, enormous design size, and short market windows have put tremendous pressure on test to occur earlier rather than later. Even at the RTL level, where hardware test typically has not ... » read more

Considerations For Choosing The Right Low-Power Tools
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Cheryl Ajluni Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use. Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as i... » read more

A High-Level Model For Reducing Frustration
By Jon McDonald - 24 Sep, 2009 - Comments: 0

By Jon McDonald Earlier this week I was sitting in the airport waiting for my flight 
to depart. I was connecting through Atlanta. This happened to be one of the days that Atlanta was receiving heavy rains causing flooding 
and occasionally closing the airport. First the flight to Atlanta was 
delayed an hour, then two, then three. Meanwhile my connecting flight 
had been c... » read more

Verification As A Deterrent?
By Ed Sperling - 24 Sep, 2009 - Comments: 0

By Ed Sperling Verification is becoming more than a bottleneck in semiconductor design. It’s actually deterring companies from adopting the latest techniques for saving power or building certain features into chips. The problem is one of complexity, and it’s getting worse at every node. While the tools exist to do complex designs, there are the classic tradeoffs of area, power and per... » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 04 Sep, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power a... » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 28 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

What’s New And What Isn’t In ESL
By Jon McDonald - 27 Aug, 2009 - Comments: 0

By Jon McDonald Just because a problem can be solved doesn’t mean it has been solved. Last week I was on a panel at the ISLPED conference in San Francisco. This conference is focused on low power, and the panel addressed some of the things that are being done and some things needed for low power analysis exploration and trade-offs. While the panel was very interesting, one question that... » read more

Restrictive Design Rules, Take Two
By Ed Sperling - 27 Aug, 2009 - Comments: 0

By Ed Sperling For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money. Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and bel... » read more

An Inside Look At Transaction-Level Power Modeling
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Ann Steffora Mutschler With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial architectural design. The only way to do that is to model power consumption at the transaction level. While power is typically estimated after RTL synthesis, the better a... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy