tag: Mentor Graphics

Making Quality A Top Priority in Next-Generation Designs
By Cheryl Ajluni - 25 Jun, 2009 - Comments: 0

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately. Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, qu... » read more

Custom IC Design: They Call This Progress?
By Ed Sperling - 25 Jun, 2009 - Comments: 0

By Ed Sperling For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes. The basic problem is that each world has functioned independently of the other from the start. They use different... » read more

Problems In Multicore Design
By Jon McDonald - 27 May, 2009 - Comments: 0

Jon McDonald talks about the multitude of choices in multicore design and what to do about it. Click here to watch the video. » read more

Pain Points At 22nm And Beyond
By Ed Sperling - 27 May, 2009 - Comments: 0

By Ed Sperling The roadmap for 22nm has a giant pothole in the middle of it. That hole is supposed to be filled by extreme ultraviolet lithography, or EUV. Instead it is being patched up using immersion lithography, which is about to cause some monumental headaches for design teams. The difference is comparable to a surgeon using a chainsaw instead of a scalpel. The cut isn’t nearly as ... » read more

Formal Verification 101
By Various Writers - 27 May, 2009 - Comments: 0

By Clive "Max" Maxfield The first time I came into contact with the concepts of a digital hardware description language (HDL) and digital logic simulation, I inherently understood how it all "worked." The idea that the statements in the modeling language acted in a concurrent manner just seemed to make sense. By comparison, trying to wrap my brain around formal verification has always mad... » read more

Is ESL Formal Verification An Oxymoron?
By Jon McDonald - 29 Apr, 2009 - Comments: 0

“No amount of experimentation can ever prove me right; a single experiment can prove me wrong.” – Albert Einstein I’ve had a number of conversations recently trying to understand what verification means for ESL and higher level models. It seems that most of the people I talk to are looking for a guarantee, they want formal verification, a proof that the design is doing what it should... » read more

Intelligent Verification Offers Hope For “Smartening” Up Verification
By Cheryl Ajluni - 28 Apr, 2009 - Comments: 0

By Cheryl Ajluni As with death and taxes, when it comes to design some things are just inevitable. For one, as design geometries shrink, design complexity will continue to increase. For another, verification is the single most time-consuming and intensive part of the entire design cycle. While new tools and methodologies have enabled designers to work through many of the existing complexity i... » read more

Soft Errors Create Tough Problems
By Ed Sperling - 28 Apr, 2009 - Comments: 0

By Ed Sperling Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore. At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alter... » read more

Moore’s Law Splinters
By Ed Sperling - 28 Apr, 2009 - Comments: 0

By Ed Sperling Moore’s Law continues progressing at a rate of one node every two years or so, but the number of companies that are adhering to that schedule is becoming much harder to pinpoint. Even the nodes themselves are becoming fuzzy. While Intel is looking at 32nm as the next node after 45nm, TSMC is looking at 28nm as the next node after 40nm. And there are likely to be extensions wi... » read more

Experts At The Table: Platform-Based Design
By Ed Sperling - 23 Apr, 2009 - Comments: 0

By Ed Sperling System-Level Design sat down with Simon Bloch, vice president and general manager of ESL/HDL Design and Synthesis at Mentor Graphics; Mike Gianfagna, vice president of marketing at Atrenta; and Jim Hogan, a private investor. What follows are excerpts of a lively, often contentious two-hour conversation.     SLD: Where does the consolidation happen in the chip design world... » read more

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