Open Source Processors: Fact Or Fiction?


Open source processors are rapidly gaining mindshare, fueled in part by early successes of RISC-V, but that interest frequently is accompanied by misinformation based on wishful thinking and a lack of understanding about what exactly open source entails. Nearly every recent conference has some mention of RISC-V in particular, and open source processors in general, whether that includes keyno... » read more

Test Chips Play Larger Role At Advanced Nodes


Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

Debugging Complex SoCs


Semiconductor Engineering sat down to discuss the debugging of complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. What follows are excerpts of ... » read more

Formally Ensuring Equivalence Between C++ And RTL Designs


Moving untimed C++ design descriptions through a High-Level Synthesis (HLS) flow, designers wonder if the generated, timed RTL is functionally equivalent to the original, high-level description. When they make refinements or optimize RTL for power, they naturally are concerned that these changes no longer meet their original specifications. They could create testbenches and run verification at ... » read more

Will Open-Source EDA Work?


Open-source EDA is back on the semiconductor industry's agenda, spurred by growing interest in open-source hardware. But whether the industry embraces the idea with enough enthusiasm to make it successful is not clear yet. One of the key sponsors of this effort is the U.S. Defense Advanced Research Projects Agency (DARPA), which is spearheading a number of programs to lower the cost of chip ... » read more

Blog Review: June 26


Arm's Krish Nathella and Dam Sunwoo dig into research to make a practical implementation of a temporal data prefetcher that overcomes the huge on- and off-chip storage and traffic overheads usually associated with them. Cadence's Paul McLellan notes that while concerns about uncover bias in computer vision algorithms usually focus on people, a team at Facebook found that object recognition t... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War


Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Who’s Responsible For Security Breaches?


Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Wrestling With High-Speed SerDes


SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

Blog Review: June 19


Mentor's Rebecca Lord digs into signal integrity complications and why today's high frequency signals make it important to understand the physics of transmission lines. Cadence's Meera Collier points to the need to recognize diversity and nuance when compiling AI training datasets and avoid the oversimplification that can lead to bias. Synopsys' Deepak Nagaria checks out the new features ... » read more

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