Hybrid Approach Emerges For Edge/Cloud Inspection Of Chips


An explosion in data from inspection images and metrology measurements is creating a confusing set of demands for chipmakers and their equipment vendors. On one hand they need the massive storage and compute resources of the cloud to utilize AI/ML-based models, but they also need the faster response time of the edge to make adjustments at the tool level. Balancing these requirements is a mas... » read more

Smarter Packaging: How AI is Reshaping Assembly and Materials Control


When a multi-die package worth $500 fails final test because of a defect that originated three process steps earlier, the economics of advanced packaging become painfully clear. Each excursion carries downstream costs that ripple across assembly, final test, and even system qualification. As packaging margins tighten, the industry is betting on artificial intelligence (AI) to catch those pro... » read more

Increasing Semiconductor Device Reliability Requires Adding More Wafer Inspection


Some industry sectors such as automotive and medical continue to push for higher and higher reliability levels; however, many fabs are having difficulties achieving them. Current inspection regimes still allow too many defects to pass through and escape to the field – primarily because of time and expense issues. Too much wafer is still left uninspected One fundamental problem is the amount... » read more

The Hidden Cost Of Contact Resistance


Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

Manufacturing At The Limits


Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

How Guardbanding Of Inline Wafer Defects Can Improve Chip Reliability Insurance


Partially defective, marginal die can still be functional enough to pass final electrical test. Some of these “walking wounded” chips get past final testing, but in the customer's end product, under ongoing stress, they may fail. This is a particularly serious issue with automotive, medical and other customers who demand maximum long-term device reliability. The semiconductor industry ha... » read more

Marginal Wafer Defects Can Slip Past Electrical Testing


Final electrical test remains one of the best ways to assess a circuit’s ultimate viability. But we know that, unfortunately, even 100% end-of-line electrical testing of semiconductor wafers will not guarantee that chips will not fail in the field. Certain non-killer but marginal wafer defects can still slip through electrical testing if they have sufficient electrical connectivity, even thou... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era


The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Chip Industry Week In Review


GlobalFoundries plans to acquire MIPS, adding RISC-V processor IP and PPA optimization software capabilities to its foundry offerings. MIPS will continue to operate as a standalone business within GF. The deal is expected to close in the second half of 2025. The EU rolled out new general-purpose AI rules this week to limit copyright infringement, protect public safety, and require transparency... » read more

Detecting Slips, Scratches, Cracks In Wafers And Dies Becoming Harder


Defect detection requirements on the order of 10 defective parts per million (DPPM) are driving improvements in inspection tools’ resolution and throughput at foundries and OSATs. However, defects that manifest as slips, scratches, and micro-cracks continue to bedevil the prevalent optical inspection methods. These defects can range in size from nanometers to millimeters, some of which are... » read more

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