tag: Moore’s law

Do We Have An IC Model Crisis?
By Brian Bailey - 27 May, 2021 - Comments: 0

Models are critical for IC design. Without them, it's impossible to perform analysis, which in turn limits optimizations. Those optimizations are especially important as semiconductors become more heterogenous, more customized, and as they are integrated into larger systems, creating a need for higher-accuracy models that require massive compute power to develop. But those factors, and other... » read more

Scaling Simulation
By Brian Bailey - 27 May, 2021 - Comments: 1

Without functional simulation the semiconductor industry would not be where it is today, but some people in the industry contend it hasn't received the attention and research it deserves, causing a stagnation in performance. Others disagree, noting that design sizes have increased by orders of magnitude while design times have shrunk, pointing to simulation remaining a suitable tool for the job... » read more

The Increasingly Uneven Race To 3nm/2nm
By Mark LaPedus and Ed Sperling - 24 May, 2021 - Comments: 2

Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

11 Ways To Reduce AI Energy Consumption
By Bryon Moyer - 13 May, 2021 - Comments: 1

As the machine-learning industry evolves, the focus has expanded from merely solving the problem to solving the problem better. “Better” often has meant accuracy or speed, but as data-center energy budgets explode and machine learning moves to the edge, energy consumption has taken its place alongside accuracy and speed as a critical issue. There are a number of approaches to neural netw... » read more

New Methodologies Create New Opportunities
By Brian Bailey - 27 Apr, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardwa... » read more

Verification In The Open Source Era
By Brian Bailey - 25 Mar, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardwa... » read more

Changing The Rules For Chip Scaling
By Ed Sperling - 10 Mar, 2021 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about the incessant drive for chip density, how to improve that density through other means than just scaling, and why this is so important for the chip industry. » read more

Die-To-Die Stress Becomes A Major Issue
By Ann Mutschler - 14 Jan, 2021 - Comments: 2

Stress is becoming more critical to identify and plan for at advanced nodes and in advanced packages, where a simple mismatch can impact performance, power, and the reliability of a device throughout its projected lifetime. In the past, the chip, package, and board in a system generally were designed separately and connected through interfaces from the die to the package, and from the packag... » read more

AI And High-NA EUV At 3/2/1nm
By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

What’s Next In AI, Chips And Masks
By Mark LaPedus - 19 Nov, 2020 - Comments: 0

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to talk about AI and Moore’s Law, lithography, and photomask technologies. What follows are excerpts of that conversation. SE: In the eBeam Initiative’s recent Luminary Survey, the participants had some interesting observations about the outlook for the photomask market. What were those observations? Fujimur... » read more

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