Inside Photomask Writing

By Mark LaPedus - 19 Jan, 2017 - Comments: 0

Hirokazu Yamada, a board member and the director of the Mask Lithography Division of NuFlare, sat down with Semiconductor Engineering to discuss photomask technology, e-beam mask writer trends and other topics. NuFlare is the world’s largest supplier of e-beam mask writers. What follows are excerpts of that conversation. SE: How does the [getkc id="265" kc_name="photomask"] market look in... » read more

Finding Defects Is Getting Harder

By Mark LaPedus - 17 Sep, 2015 - Comments: 1

Chipmakers are plotting out a strategy to scale the transistor to 10nm and beyond. Migrating to these nodes presents a number of challenges, but one issue is starting to gain more attention in the market—killer defects. Defects have always been problematic in the yield ramp for chip designs, but the ability to find them is becoming more difficult and expensive at each node. And it will be... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 28 Aug, 2015 - Comments: 0

NuFlare Technology wants to enter a new market. The e-beam giant and NGR are jointly collaborating on a development program for next-generation electron-beam wafer inspection and metrology. It’s unclear if NuFlare is developing a single- or multi-beam tool, however. Don’t look now, but a fab tool downturn could be on the horizon. This comes amid a slowdown in PCs, tablets and smartphone... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: NGR

Inside Photomask Writing

Finding Defects Is Getting Harder

The Week In Review: Manufacturing