tag: parasitic extraction

28nm FinFETs?
By Brian Bailey - 10 Jul, 2014 - Comments: 5

One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a tra... » read more

Bringing Electrical Info To Design’s Forefront
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Fixing DP Errors: Colors Or Rings
By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

How To Reduce The Need For Guardbanding A Flash ADC Design
By Various Writers - 28 Mar, 2013 - Comments: 0

For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction is critical for first silicon success. New 3D parasitic extraction technology applied to a flash ADC circ... » read more

Managing Electrical Communications Better
By Ann Mutschler - 14 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the electrical components of signal paths between IC, package, board and system is no small task, and it’s only growing in complexity. Understanding how to correctly optimize the communications within a system is critical given that the I/O power is becoming a significant portion of the overall chip power as the number of bits and the speed at which t... » read more

Double Patterning: Challenges And Possible Solutions In Parasitics Extraction
By David Abercrombie - 16 Aug, 2012 - Comments: 0

By Dusan Petranovic and David Abercrombie Double patterning (DP), as the simplest form of multi-patterning techniques, is receiving lots of attention right now. The need for double patterning techniques is driven by the physical limits of the dimensions that can be resolved with current light sources and lenses, as well as by the difficulties and delays in deploying next-generation lithography... » read more

New Reliability Issues
By Arvind Vel - 14 Jun, 2012 - Comments: 0

By Arvind Shanmugavel Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities ha... » read more

Field Solvers To The Rescue
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Pallab Chatterjee Field solvers have always been part of the Parasitic Extraction (PEX) world, but due to their long run times and complexity in configuration, their role was relegated to the setup/reference table generation for the pattern based 1-D and 2-D RC extraction tools. That’s about to change. Mentor, in combination with STMicroelectronics, one of it customers, said that at ... » read more

Expert Shootout: Parasitic Extraction
By Ed Sperling - 26 Feb, 2010 - Comments: 0

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation. LPE: What changes with at 22nm and beyond with structures like FinFETs? Robertson: It’s no... » read more

Expert Shootout: Parasitic Extraction
By Ed Sperling - 19 Feb, 2010 - Comments: 0

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation. LPE: Does parasitic extraction get more complex as we move into multicore chips? And if so, wh... » read more

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