Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding


As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

End-to-End Yield Management for Compound Semiconductors Manufacturing


Abstract: Progress in compound semiconductors is hindered by the high level of defectivity of the initial material. Here we take Silicon Carbide manufacturing technology as an example and provide an overview of manufacturing analytics tools and methodologies used to drive yield ramp and capacity expansion. We focus on 2 examples of site-to-site handoff: substrates handoff to IC front-end fab or... » read more

Chip Industry Week in Review


Apple plans to increase its U.S. investment by an additional $100 billion over four years, which includes the launch of an advanced manufacturing supply chain program, spurring a number of related chip industry announcements, including: Apple will invest in Amkor's new packaging and test facility in Arizona as its first and largest customer, and Amkor will package and test Apple silicon pr... » read more

Harnessing The Power Of Data To Remain Competitive


The semiconductor industry operates at the forefront of technological innovation, even as manufacturers face constant pressure to improve production yields, manage intricate supply chains, reduce costs and accelerate time to market. Businesses have learned to harness the power of data to optimize decision-making and streamline operations to remain competitive by using PDF Solutions' Exensio ... » read more

How Advanced Packaging Is Reshaping Inspection


As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

Full Wafer Inspection for Voltage Contrast Systematic Defects Using High-Throughput Point Scan


Abstract: A next generation system and methodology for high-throughput e-beam hot spot inspection is described. Rather than capturing images of each hot spot, just a single pixel centered on the signal node of each hot spot is collected and used to assess if the hot spot is defective or not. This innovation results in a very substantial savings in time per hot spot, and therefore a tremendous ... » read more

Tackling Advanced Chip Manufacturing Challenges


Intel and PDF Solutions are deepening their partnership to address the growing complexity of semiconductor manufacturing at advanced nodes, according to a recent discussion between Intel CEO Lip-Bu Tan and PDF Solutions CEO John Kibarian at the Direct Connect Intel Foundry event in April. During the presentation, Kibarian highlighted how the two companies have been collaborating for approxim... » read more

High-Quality Data Needed To Better Utilize Fab Data Streams


Fab operations have wrestled with big data management issues for decades. Standards help, but only if sufficient attention to detail is taken during collection. Semiconductor wafer manufacturing represents one of the most complex manufacturing processes in the world. With each generation of process improvement comes more sophisticated fab equipment, new process recipes, and exponential incre... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity


Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more

Chip Industry Week in Review


Check out the Inside Chips podcast for our behind-the-scenes analysis. Newly proposed U.S. legislation called the Chip Security Act would use location verification tracking as a tool to help combat chip smuggling. This follows a report by the Economist that showed Taiwan exports of advanced chips to Malaysia in the first quarter has nearly reached 2024 totals, heightening concerns that China... » read more

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