Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology


A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

Using Process Modeling To Enhance Device Uniformity During Self-Aligned Quadruple Patterning


Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost. This is particularly true for very simple and periodic patterns, such as line & space patterns or hole arrays. The biggest challenge of SAQP is the inherently asymmetric mask shape. This asymmetry can create structural ... » read more