Chip Industry Week in Review

By The SE Staff - 18 Jul, 2025 - Comments: 0

The U.S. government will grant licenses to NVIDIA and AMD to again sell some AI chips — NVIDIA's H20 GPU and AMD's MI308 — to Chinese companies. TrendForce projects that the availability of NVIDIA chips, in particular, will create a surge in demand from Chinese AI firms and cloud service providers, and boost high-bandwidth memory (HBM) consumption. The move could raise China’s share of... » read more

Silent Data Corruption

By Ed Sperling - 16 Jul, 2025 - Comments: 0

Everyone expects their compute systems to generate the correct answer. When they don't, it's cause for alarm, because it's not always clear how long the problem has persisted. Even worse, chips and systems are now so complex that it may require a unique sequence of operations to trigger a silent data error, and they may show up only occasionally, and maybe only after months or years of use in t... » read more

GenAI’s Breakneck Pace Is Reshaping The Semiconductor Industry

By Alex Burlak - 10 Jul, 2025 - Comments: 0

Humankind is witnessing a technological revolution so extreme that its full magnitude might extend beyond the scope of our intellect. Generative AI (GenAI) is doubling its performance every six months [1], outpacing Moore's law in what the industry calls Hyper Moore's Law. Some cloud AI chipmakers expect to double or triple performance every year for the next ten years [2]. In this three-part b... » read more

Easing The Stress For Package-Level Burn-In

By Laura Peters - 10 Jul, 2025 - Comments: 0

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and multi-chiplet packages become more common, and concerns about aging circuitry heighten, shifting stress testing to the wafer level looks increasingly attractive from a quality, throughput, and cost standp... » read more

Scaling GenAI Training And Inference Chips With Runtime Monitoring

By proteanTecs - 10 Jul, 2025 - Comments: 0

GenAI’s rapid growth is pushing the limits of semiconductor technology, demanding breakthroughs in performance, power efficiency, and reliability. Training and inference workloads for models like GPT-4 and GPT-5 require massive computational resources, leading to skyrocketing costs, energy consumption, and hardware failures. Traditional optimization methods, such as static guard bands and per... » read more

Distributing Intelligence Inside Multi-Die Assemblies

By Ed Sperling - 26 Jun, 2025 - Comments: 0

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

Challenges In Using Sub-7nm ICs In Automotive

By Laura Peters - 10 Jun, 2025 - Comments: 0

The automotive industry is producing vehicles with increasing levels of real-time decision-making, enabled by thousands of ICs, sensors, and multi-chip packages, but making sure these systems work flawlessly throughout their expected lifetimes is a growing challenge. Automotive chips traditionally were developed at mature process nodes in five- to seven-year cycles, but much has changed over... » read more

Can Your ATPG Do This? Cut Defects Escaping Detection With ML

By Alex Burlak - 10 Jun, 2025 - Comments: 0

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the silicon and ensures they are applied effectively using the chip’s Design-for-Test (DFT) infrastructure. This combination enhances fault detection while optimizing test efficiency. These patter... » read more

Rethinking Chip Reliability For Harsh Conditions

By Gregory Haley - 10 Jun, 2025 - Comments: 0

As semiconductors push into environments once considered untenable, reliability expectations are being redefined. From the vacuum of space and the inside of jet engines to deep industrial automation and electrified drivetrains, chips now must endure extreme temperature swings, corrosive atmospheres, mechanical vibration, radiation, and unpredictable power cycles, all while delivering increasing... » read more

More Data, More Redundant Interconnects

By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

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