tag: RISC-V

Open-Source Verification
By Brian Bailey - 30 Jul, 2020 - Comments: 1

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

RISC-V Gaining Traction
By Ed Sperling - 30 Jul, 2020 - Comments: 0

Part 1: Semiconductor Engineering sat down to discuss where and why RISC-V is doing well, with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are excerpt of that ... » read more

Linting RISC-V Designs
By Alex Gnusin - 30 Jul, 2020 - Comments: 0

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions and their flexibility creates a problem when choosing the most reliable and robust solution from a number of contenders. Sure, a RISC-V IP design must be compliant to basic ISA standards and should contain a testing suite demonstrating that compliance. But sh... » read more

Challenges For A Post-Moore’s Law World
By Ed Sperling - 27 Jul, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss challenges at the edge, the impact of open-source, and how to attract new talent, with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The con... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 Jul, 2020 - Comments: 0

Perforce Software acquired Methodics. Founded in 2006 and based in San Francisco, Methodics' IP lifecycle management and traceability software will join Perforce's larger portfolio of DevOps software that includes version control, Agile planning, and static code analysis. The two companies have had a strategic partnership in place with customers using software from both companies. Terms of the ... » read more

Smaller Nodes, Much Bigger Problems
By Ed Sperling - 15 Jul, 2020 - Comments: 3

João Geada, chief technologist at Ansys, sat down with Semiconductor Engineering to talk about device scaling, advanced packaging, increasing complexity and the growing role of AI. What follows are excerpts of that conversation. SE: We've been pushing along Moore's Law for roughly a half-century. What sorts of problems are you seeing now that you didn't see a couple nodes ago? Geada: The... » read more

Winners And Losers At The Edge
By Ed Sperling - 01 Jul, 2020 - Comments: 0

The edge is a vast collection of niches tied to narrow vertical markets, and it is likely to stay that way for years to come. This is both good and bad for semiconductor companies, depending upon where they sit in the ecosystem and their ability to adapt to a constantly shifting landscape. Some segments will see continued or new growth, including EDA, manufacturing equipment, IP, security an... » read more

Open-Source Hardware Momentum Builds
By Brian Bailey - 25 Jun, 2020 - Comments: 2

Open-source hardware continues to gain ground, spearheaded by RISC-V — despite the fact that this processor technology is neither free nor simple to use. Nevertheless, the open-source hardware movement has established a solid foothold after multiple prior forays that yielded only limited success, even for processors. With demand for more customized hardware, and a growing field of startups... » read more

About The SweRV Core EH2
By Roddy Urquhart - 25 Jun, 2020 - Comments: 0

In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2? ... » read more

Simplifying And Speeding Up Verification
By Ed Sperling - 16 Jun, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

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