tag: Siemens EDA

Packetized Scan Test Delivery
By Geir Eide - 06 Jul, 2021 - Comments: 0

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To address these challenges, we now have the option of implementing a packetized data network for scan test that moves the scan data through the SoC much more efficiently than the traditional pin-... » read more

Week In Review: Design, Low Power
By Jesse Allen - 02 Jul, 2021 - Comments: 0

Tools Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (st... » read more

‘Hug The Debug’ – Before It’s Too Late
By Sumit Vishwakarma - 01 Jul, 2021 - Comments: 0

Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by a global chip shortage, especially in the automotive industry. Manufacturing a robust chip is a long, iterative process that may require many re-spins. Shift-left refers... » read more

Automotive Safety Island
By Siemens EDA - 01 Jul, 2021 - Comments: 0

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. Automotive ICs, once deployed for simple functions like controlling windows, are now performing complex functions related to advanced driver-assist systems (ADAS) and autonomous driving applications. The processing power required results in very large and complex ICs that ... » read more

Blog Review: June 30
By Jesse Allen - 30 Jun, 2021 - Comments: 0

Siemens EDA's Chris Spear considers what classes should represent in SystemVerilog and offers two major categories along with some helpful UVM tips. Cadence's Paul McLellan listens in on keynotes at the recent TSMC Technology Symposium, including TSMC CEO C. C. Wei's introduction some of the fab's new offerings, such as an automotive-focused N5 process. Synopsys' Dennis Kengo Oka notes th... » read more

Debug: The Schedule Killer
By Brian Bailey - 30 Jun, 2021 - Comments: 0

Debug often has been labeled the curse of management and schedules. It is considered unpredictable and often can happen close to the end of the development cycle, or even after – leading to frantic attempts at work-arounds. And the problem is growing. "Historically, about 40% of time is spent in debug, and that aspect is becoming more complex," says Vijay Chobisa, director of product manag... » read more

Data Centers On Wheels
By Ann Mutschler - 28 Jun, 2021 - Comments: 2

Automotive architectures are evolving quickly from domain-based to zonal, leveraging the same kind of high-performance computing now found in data centers to make split-second decisions on the road. This is the third major shift in automotive architectures in the past five years, and it's one that centralizes processing using 7nm and 5nm technology, specialized accelerators, high-speed memor... » read more

Rocky Road To Designing Chips In The Cloud
By Ann Mutschler - 24 Jun, 2021 - Comments: 0

EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach. By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip desig... » read more

Shifting Left: Early Multi Physics Analysis For STCO
By Per Viklund - 24 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the emergence of a system technology co-optimization (STCO) approach, in which an SoC is disaggregated into smaller modules (also known as chiplets) that can be asynchronously desi... » read more

Architectural Considerations For AI
By Brian Bailey - 24 Jun, 2021 - Comments: 2

Custom chips, labeled as artificial intelligence (AI) or machine learning (ML), are appearing on a weekly basis, each claiming to be 10X faster than existing devices or consume 1/10 the power. Whether that is enough to dethrone existing architectures, such as GPUs and FPGAs, or whether they will survive alongside those architectures isn't clear yet. The problem, or the opportunity, is that t... » read more

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