tag: Siemens EDA

Adapting Formal
By Ann Mutschler - 09 Feb, 2017 - Comments: 2

With more pressure to make designs efficient — from a power perspective, as well as from an overall design view — finding what can be removed from a design is one step closer. As discussed in the article published today, “What Can Be Cut From A Design?” — sequential analysis, based on formal verification technology, is gaining traction. I specifically asked Mentor Graphics’ direc... » read more

Devices Threatened By Analog Content?
By Brian Bailey - 09 Feb, 2017 - Comments: 0

As the amount of analog content in connected devices explodes, ensuring that the analog portion works properly has taken on a new level of urgency. Analog circuitry is required for interpreting the physical world and for moving data to other parts of the system, while digital circuitry is the fastest way to process it. So a sensor that gives a faulty reading in a car moving at high speed or ... » read more

What Can Be Cut From A Design?
By Ann Mutschler - 09 Feb, 2017 - Comments: 0

A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it. This shift is happening at every level, from the initial design to implementation. After years of trying to fill every square nanometer of real estate on a piece of silicon with memory and logic, doubling the number of [getkc id="26" kc_name="transistors"] from on... » read more

Finding The Unexpected In High Performance Designs
By Russell Klein - 09 Feb, 2017 - Comments: 0

It was growing dark as I drove a winding road on Mt. Hood, deep in the American northwest forest. The firs were thick, creating a lot of shadows and making it tough to see things clearly. Then out of the corner of my eye, I swear I saw a 10-foot “man” covered with brown fur. It looked a lot like a Wookie. But everyone knows Wookies aren’t real. It had to be Bigfoot! I slammed on th... » read more

How Formal Reduces Fault Analysis For ISO 26262
By Mentor, a Siemens Business - 08 Feb, 2017 - Comments: 0

The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult. Unlike simulation where it is never known if the design has been simulated enough or given enough input, formal verification conclusively determines if faults are safe or not, making ... » read more

Blog Review: Feb. 8
By Jesse Allen - 08 Feb, 2017 - Comments: 0

Mentor's Craig Armenti looks at some of the challenges involved with multi-board PCB or system design. Cadence's Paul McLellan highlights a presentation by Igor Keller on the state of the art in static timing analysis. Synopsys' Eric Huang has some ideas for USB interoperability testing. Intel's Ron Wilson delves into the current state of 5G, and why perspectives on that differ. Ans... » read more

Implementing Fan-Out Wafer-Level Packaging with Mentor Graphics
By Mentor, a Siemens Business - 06 Feb, 2017 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a new high-density packaging technology that is rapidly gaining popularity. What is it? Who needs it? How do you take advantage of it? What limitations does it have? Learn all about FOWLP and our comprehensive tool integration and support for the design and verification of FOWLP products. To read more, click here. » read more

Chip-Package-Board Issues Grow
By Ann Mutschler - 06 Feb, 2017 - Comments: 0

As systems migrate from a single die in a single package on a board, to multiple dies with multiple packaging options and multiple PCB form factors, it is becoming critical to move system planning, assembly, and optimization much earlier in the design-through-manufacturing flow. This is easier said than done. Multiple tools and operating systems are now used at each phase of the flow, partic... » read more

Betting On Wafer-Level Fan-Outs
By Ed Sperling - 06 Feb, 2017 - Comments: 2

Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

Uncovering Unintended Behavior
By Brian Bailey - 03 Feb, 2017 - Comments: 0

Very few companies ever had to worry about security until recently. Over the past couple of years, we have seen increasing evidence that our connected systems are vulnerable. The recent distributed denial of service (DDoS) attack, which made many Internet sites unavailable, has focused attention on Internet of Things (IoT) devices such as digital video recorders and cameras that have Internet a... » read more

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