tag: Siemens EDA

IP Qualification During RTL Synthesis
By Sudhakar Jilla - 23 Feb, 2017 - Comments: 0

By Sudhakar Jilla and Arvind Narayanan The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical design, which can introduce unwanted schedule risk into the design process. Much of the risk of IP development can be mitigated by using new physical synthesis... » read more

Custom Hardware Thriving
By Ann Mutschler - 23 Feb, 2017 - Comments: 0

In the early days of the IoT, predictions about the commoditization of hardware and the end of customized hardware were everywhere. Several years later, those predictions are being proven wrong. Off-the-shelf components have not replaced customized hardware, and software has not dictated all designs. In fact, in many cases the exact opposite has happened. And where software does play an elev... » read more

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

IP Qualification with Oasys-RTL
By Mentor, a Siemens Business - 22 Feb, 2017 - Comments: 0

With increasing design sizes and complexities, the use of IP (intellectual property) as basic building blocks for better SoC design is also increasing. This paper presents the challenges faced during IP integration at the SoC level and what can be done to mitigate those risks during IP development. Mentor’s Oasys-RTL RTL floorplanning and physical synthesis tool offers a unique IP qualificati... » read more

Blog Review: Feb. 22
By Jesse Allen - 22 Feb, 2017 - Comments: 0

Mentor's Brian Derrick digs into the state of the electric vehicle industry and whether established OEMs will be able to make the changes required to meet new consumer demands. Cadence's Paul McLellan listens in on how to greatly improve the efficiency of machine learning, without using custom hardware, in a talk by Stanford's Kunle Olukotun. Synopsys' Robert Vamosi warns not to overlook ... » read more

The Week In Review: IoT
By Jeff Dorsch - 17 Feb, 2017 - Comments: 0

Consortia Optimal+ said this week that it has joined the Industrial Internet Consortium. “The Industrial Internet of Things (IIoT) will have a tremendous impact on industries worldwide. The application of smart manufacturing, combined with the collection and analysis of in-use/field stage data, will deliver powerful insights to brand owners and enable them to achieve dramatic improvements in... » read more

The Week In Review: Design
By Jesse Allen - 17 Feb, 2017 - Comments: 0

Tools Mentor Graphics launched the company's third generation data-center friendly emulation platform, Veloce Strato. The emulator has a capacity of 2.5BG when fully loaded, and total capacity can be increased by linking emulators. It has available slots for 64 Advanced Verification Boards (AVBs) and fully loaded consumes up to 50KW (22.7 W/Mgate) of power. Aldec uncorked the latest versi... » read more

Battling Fab Cycle Times
By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

ECO Fill Can Rescue Your SoC Tapeout Schedule
By Vikas Gupta - 16 Feb, 2017 - Comments: 0

By Vikas Gupta and Bhavani Prasad Integrated circuit (IC) design and manufacturing is one of the most challenging engineering industries. As soon as a design engineer gets into “the groove” and feels comfortable taping out in a particular technology node, the next technology node shrink is already there to pose a new and greater set of challenges. While it almost goes without saying that... » read more

Blog Review: Feb. 15
By Jesse Allen - 15 Feb, 2017 - Comments: 0

Mentor's Jean-Marie Brunet looks at factors driving the growth of hardware emulation for SoCs. Cadence's Dave Pursley asserts that the role of hardware developers is about to change for the better. Synopsys' Robert Vamosi says that major software vulnerabilities are becoming less frequent, in spite of hype surrounding named bugs. ARM's Rhonda Dirvin discusses the release of the OpenFog... » read more

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