Preparing For The IoT Data Tsunami


Engineering teams are facing a flood of data that will be generated by the [getkc id="76" comment="Internet of Things"], both from the chip design side and from the infrastructure required to handle that data. There are several factors that make this problem particularly difficult to deal with. First, there is no single data type, which means data has to be translated somehow into a usable f... » read more

The Week In Review: Design/IoT


Tools Synopsys incorporated automated analog and mixed-signal debug capabilities into its Verdi SoC debug platform, which now provides comprehensive hierarchical and schematic views of both the analog and digital portions of designs and automated tracing across analog and digital blocks. Mentor announced three applications for the Veloce emulation platform focused on overcoming unpredicta... » read more

Racing To Design Chips Faster


A shift is underway to develop chips for more narrowly defined market segments, and in much smaller production runs. Rather than focusing on shrinking features and reducing cost per transistor by the billions of units, the emphasis behind this shift is less about scale and much more about optimization for specific markets and delivering those solutions more quickly. As automotive, consumer e... » read more

IP Requirements Changing


Twenty years ago the electronics industry became interested in the notion of formalizing re-use through third-party IP. It has turned out to be harder than anyone imagined. In 1996, the Virtual Socket Interface Alliance ([getentity id="22845" comment="VSIA"]) was formed to standardize the development, distribution and licensing of IP. Soon afterward, companies with a couple of people in a ga... » read more

Masters Of Abstraction


Good system designers are a unique breed. While it's easy enough to distinguish the traits that define a good one from a weak one, it's much harder to determine who possesses those traits before they are put to the test, or whether or how they can be taught. However, there is definitely a particular perspective that good system designers hold in common. The key is the ability to work with ma... » read more

Can You Really Fry an Egg on a CPU?


Solving complex thermal models with computational fluid dynamics (CFD) requires a lot of processing power, and a central processing unit (CPU) under full load generates a fair amount of heat. But can you cook an egg on it? Search online and you can find videos of people attempting to cook on their processors—I wouldn’t recommend this as a cooling solution. However, just out of curiosity, I ... » read more

The Ultimate Shift Left


Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several semiconductor development teams, especially those in Fortune 500 companies, who do not have time to change their design process. They often cite various reasons such as: • Too busy with the current project. • What we have is working, so... » read more

Getting Formal About Debug


While much of the design and verification flows have been automated, debug remains the problem child. It has defied automation and presents a management nightmare due to the variability of the process. In recent articles about debug, we examined how much time development teams spend in the debug process and some of the reasons why it is becoming a bigger problem. This includes issues such as ex... » read more

Thermal Characterization of Complex Electronics


This whitepaper describes the role of thermal transient measurement to characterize semiconductor thermal behavior. It focuses on the value measurement derived structure functions provide through interpretation of the heat flow path inside a package for use in thermal characterization, failure diagnosis, and improving simulation thermal model accuracy. Structure functions transform thermal t... » read more

Blog Review: Feb. 24


Synopsys' Graham Etchells digs through the toolbox and finds that schematic PCells can be vital in helping layout engineers tackle FinFET complexity. Cadence's Paul McLellan looks at two techniques to test the increasing number of digital gates on an automotive chip with only two pins. In the latest PCB Tech Talk Podcast, Mentor's John McMillan discusses where collaboration with MCAD fits... » read more

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