Resetting Expectations On Multi-Patterning Decomposition And Checking


As I said in Part 1 of this topic, it never ceases to amaze me how much confusion and misunderstanding there is when it comes to multi-patterning (MP) decomposition and checking. That entire first article only focused on the typical subjects I’ve had to discuss with customers regarding double-patterning (DP). I have to tell you that with the deployment of triple-patterning (TP) and quadruple-... » read more

Blog Review: Dec. 16


Power from nuclear fusion just made the leap from sci-fi to the real world in this week's top five engineering tech picks by Ansys' Bill Vandermark. Plus, stacking chips tall, helping gunshot victims survive, and a shoe just for you. A world without paralysis? Rambus' Aharon Etengoff takes a look at one research group's latest advancement, a brain implant that allowed a paralyzed man to bypa... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions Zuken acquired one of its USA resellers, electrical applications provider Caetek. The company also developed software for harness manufacturers that integrated with Zuken's electrical wiring, control systems and fluid engineering toolset. The NXP-Freescale merger is, at last, official. The largest revenue source for the combined company will be automotive, proje... » read more

How To Choose A Processor


Choosing a processor might seem straightforward at first glance, but like many engineering challenges it's harder than it looks. When is a CPU better than a GPU, MCU, DSP or other type of processor? And for what design—or part of a design? For decades, the CPU has been the default choice. “It is deliberately designed to be pretty efficient at all tasks, is straightforward to program, ... » read more

Chasing After Phantom Power


A lot of effort is being invested in power reduction techniques for mobile devices, where battery life is an important buying decision and power can translate into heat that can make a device uncomfortable to use. But are people willing to pay more for a device that consumes less power if it's plugged into a wall? And even if they are concerned about the power drawn during operation, what ab... » read more

Micro-Architectural Exploration For Low Power Design


By Abhishek Ranjan, Saurabh Shrimal and Sanjiv Narayan In the first part of this series, we discussed the need to perform power optimizations and exploration at higher levels of abstractions, where the potential to reduce the power consumption was highest. While fine-grained local changes (like clock-gating, operand isolation, etc.) for power reduction are well understood and widely adopted,... » read more

Power Aware CDC Verification Of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts


Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic. We will discuss the effects of advanced low power design on CDC design and verification. This paper describes the new CDC issues caused by the addition of power control logic including isolation cells, retention cells, lev... » read more

Blog Review: Dec. 9


From spring-loaded knees to modular planes to a two-seater drone, there's a new world of transportation in this week's top engineering and technology picks from Ansys' Justin Nescott. As for disappearing worlds, check out the sun-like star getting eaten by a black hole. Cadence's Paul McLellan takes a look back at archaic terminology and even older standards, with a brief history of Calma to... » read more

Defining Sufficient Coverage


Semiconductor engineering sat down to discuss the definition of sufficiency of coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"]; Larry Vivolo was, at the time of this roundtable, senior director of product marketing for [get... » read more

The Week In Review: Design/IoT


Tools Cadence uncorked the next generation of its custom design platform optimized for advanced 10nm FinFET designs. Features include multi-patterning and color-aware layout, electrically aware design, and module generator (ModGen)-based device array flow. Deals San'an IC will provide Mentor Graphics' design rule decks to its customers to help verify that their mobile and wireless gall... » read more

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