Blog Review: July 26


Mentor's Dan Driscoll digs into designing for safety and security on the Xilinx UltraScale+ MPSoC and the different mechanisms that support subsystem isolation. Cadence's Paul McLellan listens in on a talk by Bosch's Volkmar Denner on the future of communications and AI in connected autos. Synopsys' Robert Vamosi points to a recently-discovered vulnerability that could be present in thous... » read more

Machine Learning Popularity Grows


Machine learning and deep learning are showing a sharp growth trajectory in many industries. Even the semiconductor industry, which generally has resisted this technology, is starting to changing its tune. Both [getkc id="305" kc_name="machine learning"] (ML) and deep learning (DL) have been successfully used for image recognition in autonomous driving, speech recognition in natural langua... » read more

The Week In Review: Design


Tools Mentor released the latest version of its FloTHERM CFD software for electronics cooling simulation, adding a new design window to create and solve variants of a model with features to improve scenario definition and design space exploration. Other enhancements include support for Phase Change Materials, more abilities for PCB designs, and an improved parallel solver. Markets IC Insig... » read more

Blog Review: July 19


Synopsys' Prishkrit Abrol provides a detailed explanation of how the USB Type-C connector works. Mentor's Ricardo Anguiano examines how the RISC-V ecosystem is expanding and latest developments in the open source toolchain. Cadence's Gopi Krishnamurthy explains the lane margining requirements of the PCIe 4.0 specification. ARM's Chet Babla unravels some claims about Narrowband IoT, Cat... » read more

Hybrid Emulation


Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Dealing With System-Level Power


Analyzing and managing power at the system level is becoming more difficult and more important—and slow to catch on. There are several reasons for this. First, design automation tools have lagged behind an understanding of what needs to be done. Second, modeling languages and standards are still in flux, and what exists today is considered inadequate. And third, while system-level power ha... » read more

The Week In Review: Design


M&A Ansys acquired Computational Engineering International (CEI), the developer of a suite of products that helps analyze, visualize and communicate simulation data. Founded in 1994 as a spin-off from Cray Research, the company's program covers a wide range of data formats. Terms of the deal were not disclosed. IP Efabless launched an open source framework that allows community members... » read more

Estimating Power And Performing Optimization


Power analysis and optimization have gained importance over the last few years. During this time it has become obvious how critical it is to use realistic payloads to accurately estimate power and perform optimization tasks. Designers have a range of different objectives and concerns when it comes to power. On one side, a team wants to ensure that the average power of their chip is low enough t... » read more

IoT Myth Busting


The [getkc id="76" comment="Internet of Things"] (IoT) means many things to a large number of people, but one thing is clear—every discussion involving the IoT invariably includes some rather dramatic growth predictions for how many connected devices will be sold and who will be the primary beneficiaries. While that data helps spice up speeches, and typically gets people to read and quote ... » read more

Transistor Aging Intensifies At 10/7nm And Below


Transistor aging and reliability are becoming much more troublesome for design teams at 10nm and below. Concepts like ‘infant mortality’ and 'bathtub curves' are not new to semiconductor design, but they largely dropped out of sight as methodologies and EDA tools improved. To get past infant mortality, a burn-in process would be done, particularly for memories. And for reliability, which... » read more

← Older posts Newer posts →