tag: Synopsys

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Week In Review: Manufacturing, Test
By Linda Christensen - 24 Sep, 2021 - Comments: 1

Markets Worldwide semiconductor industry revenue is expected to grow 17.3% in 2021, compared with 10.8% in 2020, according to a new IDC report. Segment breakdown is as follows: [table id=5 /] “Semiconductor wafer prices increased in 1H21 and IDC expects increases to continue for the rest of 2021 due to material costs and opportunity cost in mature process technologies. Overall, IDC pre... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 Sep, 2021 - Comments: 0

U.S. government officials met with semiconductor industry companies and automakers to request supply chain information it hopes could address the current semiconductor shortage, Reuters reports. Secretary of Commerce Gina Raimondo hopes the information will enable them and industry to "get more granular into the bottlenecks and then ultimately predict challenges before they happen," but also wa... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 24 Sep, 2021 - Comments: 0

Automotive Cadence announced its new platform for speeding up the creation of virtual and hybrid prototypes of complex systems, such as those found in automotive systems. The Cadence Helium Virtual and Hybrid Studio enables teams to verify embedded software and firmware on virtual and hybrid configurations before the RTL is ready, in systems where software and hardware need to be created simul... » read more

Optimization Driving Changes In Microarchitectures
By Ann Mutschler - 23 Sep, 2021 - Comments: 0

The semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of AI, and the need for differentiation and customization in leading-edge applications. In the past, much of this would have been accomplished by moving to the next process node. But with the benefits from scaling diminishing at each new node, the focus is s... » read more

Building Complex Chips That Last Longer
By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Hyper-Convergence Is The New Normal For Digital Implementation
By Yudhan Rajoo - 23 Sep, 2021 - Comments: 0

The era of smart-everything has led to a surge in the need for semiconductor devices across a myriad of traditional and novel applications. These applications demand high performance yet energy-efficient compute over blazing-fast networks to service trillions of edge devices that are constantly consuming and generating large amounts of data. This surge has invigorated system architects to innov... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects
By Ann Mutschler - 22 Sep, 2021 - Comments: 0

Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

Blog Review: Sept. 22
By Jesse Allen - 22 Sep, 2021 - Comments: 0

Ansys' Tyler Ferris describes some of the many ways electronics on a PCB assembly can fail, from component level failures like wirebond breaking and liftoff to board-level failures such as conductive anodic filament failure. Cadence's Paul McLellan considers the switch from low-speed parallel interfaces to high-speed serial interfaces as one of the key advancements making modern data centers... » read more

Faster Analog Design Closure With Early Parasitic Analysis Flow – Part 1
By Synopsys - 22 Sep, 2021 - Comments: 0

In part 1 of this series, Denis Goinard, Director of Engineering at Synopsys, discusses how Synopsys provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence. Click here to play the video. Note: This is a Synopsys 'video white paper.' For more video white papers, click h... » read more

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