tag: Synopsys

Machine Learning Enabled Root Cause Analysis For Low Power Verification
By Himanshu Bhatt - 13 Jul, 2020 - Comments: 0

By Himanshu Bhatt and Susantha Wijesekara Next-generation SoCs with advanced graphics, computing and artificial intelligence capabilities are posing unforeseen challenges in verification. Designers and verification engineers using static verification technologies for low power often see many violations in the initial stages. Efficient debugging and determining root cause is a real issue and ... » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 Jul, 2020 - Comments: 0

Arm plans to double down on its core IP business and transfer its two IoT Services Group (ISG) businesses, IoT Platform and Treasure Data, to new entities that would be owned and operated by SoftBank. “SoftBank’s experience in managing fast-growing, early-stage businesses would enable ISG to maximize its value in capturing the data opportunity," said Arm CEO Simon Segars. "Arm would be in a... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 10 Jul, 2020 - Comments: 0

IoT Arm is proposing to transfer its two IoT divisions to SoftBank Group Corp., which will own and operate them under new entities. The two IoT Services Group (ISG) businesses are IoT Platform and Treasure Data. Arm intends to focus more on its IP roadmap in data and compute, once the transfer becomes finalized. It is subject to more board review. “Arm believes there are great opportunities ... » read more

Moving Data And Computing Closer Together
By Bryon Moyer - 09 Jul, 2020 - Comments: 2

The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Blog Review: July 8
By Jesse Allen - 08 Jul, 2020 - Comments: 0

Cadence's Paul McLellan profiles Alessandra Nardi, recipient of this year's Marie R. Pistilli Women in EDA award, how she entered the industry and her latest work on automotive and a functional safety language. In a video, Mentor's Colin Walls checks out why RISC-V is the hot new fashion in embedded systems development. A Synopsys writer explains why the MACsec security protocol is so imp... » read more

Shift Left Verification With Comprehensive Lint Signoff
By Synopsys - 08 Jul, 2020 - Comments: 0

With soaring complexity and continuously increasing chip sizes, achieving efficient and predictable design closure has become a prominent challenge among designers today. Demand for a faster time to market is forcing designers to find ways to shorten design cycles with accurate, efficient, one-time RTL to silicon. To meet these requirements designers are looking to implement early ”shift left... » read more

Advanced Packaging Makes Testing More Complex
By Bryon Moyer - 07 Jul, 2020 - Comments: 1

The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Monitoring IC Abnormalities Before Failures
By Anne Meixner - 07 Jul, 2020 - Comments: 0

The rising complexities of semiconductor processes and design are driving an increasing use of on-chip monitors to support data analytics from an IC’s birth through its end of life — no matter how long that projected lifespan. Engineers have long used on-chip circuitry to assist with manufacturing test, silicon debug and failure analysis. Providing visibility and controllability of inter... » read more

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