tag: Synopsys

Enabling Automotive Design
By Ann Mutschler - 07 Dec, 2017 - Comments: 0

Falling automotive electronics prices, propelled by advances in chip manufacturing and innovations on the design side, are driving a whole new level of demand across the automotive industry. Innovations that were introduced at the luxury end of the car market over the past couple years already are being implemented in more standard vehicles. The single biggest driver of change in the automo... » read more

Blog Review: Dec. 6
By Jesse Allen - 06 Dec, 2017 - Comments: 0

Synopsys' Eric Huang examines electromagnetic interference, the Bit Error Rate in USB 3.2 and how different transfer types handle errors. Mentor's Nitin Bhagwath points out several things that can cause DDR signals to behave badly, from excessive ringing to stubs in the channel. Cadence's Paul McLellan listens in as Oski CEO Vigyan Singhal explains the basics of assertion-based verificati... » read more

Which Verification Engine? (Part 2)
By Ed Sperling - 06 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

Prototyping Partitioning Problems
By Ann Mutschler - 30 Nov, 2017 - Comments: 0

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

Going On A Quest
By Tom De Schutter - 30 Nov, 2017 - Comments: 0

Over the extended Thanksgiving weekend, I went with my family to a hotel with built-in entertainment. The hotel had so many amenities as to make sure that you would never want to leave it: a water park, an arcade, multiple restaurants, miniature golf, and the list goes on. The water park was the main attraction and ensured multiple hours of fun for the entire family each day. A wave pool, in... » read more

Understanding How To Assess Tool Confidence Levels For ISO 26262
By Synopsys - 29 Nov, 2017 - Comments: 0

ISO 26262, the automotive functional safety standard, requires the assessment of software Tool Confidence Levels (TCLs). Some SoC designers are under the impression that all tools must be classified with a TCL1. In reality, the goal is to classify your tools accurately for your specific situation and use case. This white paper provides insight on assessing TCLs that are consistent with ISO 2626... » read more

Blog Review: Nov. 29
By Ed Sperling - 29 Nov, 2017 - Comments: 0

ANSYS' Robert Harwood offers a reminder that autonomous and assisted driving technology are still very much works in progress, and flawed ones at that. It will take an estimated 5 billion to 10 billion road miles to effectively train self-driving algorithms. So far, Google has logged about 3.5 million miles. Along the same lines, Mentor's Paul Johnston takes a look at the electric car market... » read more

Week In Review: Design
By Linda Christensen - 22 Nov, 2017 - Comments: 0

Acquisitions Marvell signed a definitive agreement to buy Cavium for roughly $6 billion. The deal is expected to close in mid-2018. The Cavium deal fits squarely on the cloud side and gives Marvell a much bigger reach into enterprise networking and infrastructure, as well as some developing markets. Siemens paid an undisclosed price to buy Solido Design Automation, which tracks variation i... » read more

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