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Reducing Simulation Regression Turnaround Time With Dynamic Performance Optimization


No single step in the development of semiconductor devices is more sensitive to speed than functional simulation. A modern system-on-chip (SoC) design simulates billions of cycles of operation in the process of completing the verification plan and achieving coverage goals. To validate full system functionality, many of these simulations include running code on one or more embedded processors. E... » read more

Battling Fab Cycle Times


The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more