tag: verification

Enabling Test Portability With Graphs
By Ann Mutschler - 20 Mar, 2014 - Comments: 0

Is it time to move up again? When it comes to test portability between simulation, emulation, prototypes and silicon, as well as an easier way to create a test structure, the answer appears to be a resounding ‘Yes.’ Looking at these activities from a higher level of abstraction and using a graph-based approach should allow automation where there has been none previously, and could allow val... » read more

The Week In Review: Design
By Ed Sperling - 14 Mar, 2014 - Comments: 0

Tools Synopsys uncorked the next version of its verification tool, which includes static and formal verification, new debug capabilities, and low-power and X-propagation simulation. The company says the new tool offers up to 5X performance improvement. Cadence rolled out a new version of its verification solution for designs using ARM’s interconnect IP, speeding up verification and analys... » read more

Pointing Fingers In Verification
By Brian Bailey - 12 Mar, 2014 - Comments: 11

With most EDA tools, the buying decision is related to improved quality of results or increased productivity. Will a new synthesis or clock optimization tool enable designers to do more, faster and are those gains worth the price? The equation is fairly simple. When it comes to verification tools, things are more complex. You can still make productivity gains, or purchase an additional tool ... » read more

Big Shift In SoC Verification
By Ed Sperling - 06 Mar, 2014 - Comments: 5

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

The Week In Review: Design
By Ed Sperling - 28 Feb, 2014 - Comments: 0

Tools Cadence rolled out a new verification planning and management tool that is based on SQL, which greatly improves functionality and performance and offers multi-user, multi-engine and multi-analysis capabilities. Database technology—in this case, Structured Query Language—remains one of the very few software platforms that can harness multiple processors effectively. Synopsys unveil... » read more

Abstractions: The Good, Bad And Ugly
By Ed Sperling - 27 Feb, 2014 - Comments: 0

Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Design And Verification Survey Results
By Graham Bell - 27 Feb, 2014 - Comments: 1

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins. This year, I would like ... » read more

Maximizing Verification Effectiveness Using Metric-Driven Verification
By Various Writers - 26 Feb, 2014 - Comments: 0

This paper introduces the Cadence Incisive Verification Kit as a golden example of how to maximize verification effectiveness by applying metric-driven verification (MDV) in conjunction with the Universal Verification Methodology (UVM). MDV provides an overarching approach to the verification problem by transforming an open-ended, open-loop verification process into a manageable, repeatable, de... » read more

Does It Take A Catastrophe?
By Linda Prowse Fosler - 20 Feb, 2014 - Comments: 0

What makes a company search for new verification methods and tools? Sometimes organizations change, proactively, because they are wise and want to avoid problems; but sadly, more often it is a catastrophe that forces change. This was the case with a large U.S. supplier of safety-critical and high-reliability ICs. After a failed chip, it finally moved from simply verifying the analog and digi... » read more

Executive Insight: Kathryn Kranen
By Ed Sperling - 17 Feb, 2014 - Comments: 0

Semiconductor Engineering sat down with Kathryn Kranen, president and CEO of Jasper Design Automation, to discuss what's changing in the semiconductor industry, why that's happening, and what to watch out for. The interview is part of an ongoing series of in-depth interviews with top executives from all segments of the industry. SE: What keeps you up at night? Kranen: Figuring out ways to... » read more

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