tag: verification

Experts At The Table: Performance Analysis
By Ed Sperling - 02 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

FPGA Verification with Assertions: Why Bother?
By Various Writers - 27 Jul, 2013 - Comments: 0

This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions. To download this white paper, click here. » read more

Unifying Hardware-Assisted Verification And Validation Using UVM And Emulation
By Various Writers - 25 Jul, 2013 - Comments: 0

Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification and validation platforms have been developed as separate flows, preventing reuse of modules and methods between the two. As a consequence, various customized verification and validatio... » read more

Unifying Hardware-Assisted Verification And Validation Using UVM And Emulation
By Various Writers - 25 Jul, 2013 - Comments: 0

Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification and validation platforms have been developed as separate flows, preventing reuse of modules and methods between the two. As a consequence, various customized verification and validatio... » read more

What Really Matters: User Care-Abouts In Hardware-Assisted Verification
By Frank Schirrmeister - 24 Jul, 2013 - Comments: 0

By Frank Schirrmeister Sports analogies often work well and, most certainly, they do for electronics development. When again I ran across the VISA advertisement in which Dick Fosbury is featured with his win in the high-jump competition at the 1968 Summer Olympics, I had to smile as it reminded me of hardware-assisted verification (I know, I know…twisted, you might say). Just as Fosbury chan... » read more

The Week In Review: July 22
By Mark LaPedus - 22 Jul, 2013 - Comments: 0

By Mark LaPedus ASML Holding has been under pressure to bring extreme ultraviolet (EUV) lithography into mass production. EUV is still delayed. Now, in their latest roadmaps, leading-edge chipmakers are counting on ASML’s 300mm EUV scanner for insertion at the 10nm node. Yet, at the same time, ASML also is working on a 450mm version of the EUV tool. “EUV (on 300mm) is a higher priority th... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 19 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: When it comes... » read more

Executive Briefing: Prakash Narain
By Ed Sperling - 12 Jul, 2013 - Comments: 0

Real Intent CEO Prakash Narain talks with System-Level Design about where are the pain points in verification; different types of signoff; the impact of third-party IP, and can the tools industry keep up with the rising complexity in semiconductor design. [youtube vid=C25VMRDXGAQ] » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 12 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: Is it possib... » read more

The Controversial Spec
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler Design sophistication and complexity has made it increasingly difficult to fully specify the expected behavior of a block in an SoC, but this is necessary for design and verification teams. How do you write a “good” and “complete” specification of functionality? It turns out that the discussion of defining what a good and complete specification is and how t... » read more

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