tag: verification

IP Risk Sharing
By Brian Bailey - 10 Mar, 2016 - Comments: 0

For most people within the semiconductor industry, managing risk involves making the right product decisions that will enable a company to be profitable, and ensuring the product is successfully produced within the necessary time window. In contrast, for products within high-risk areas such as medical and mil/aero, design often proceeds at a slower pace, using proven technologies and adopting l... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Power — Usage Shift Leads to Methodology Shift
By Mentor, a Siemens Business - 09 Mar, 2016 - Comments: 0

Power exploration and accurate power calculation of SoCs in the target application environment is getting executive attention due to the fact that companies are missing market windows because of power issues. This makes system-level power analysis and management a key measurement. Verification solutions that provide accurate power analysis data early are critical to making design decisions that... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Seeing Debug for What It Is
By Neil Johnson - 29 Feb, 2016 - Comments: 0

Debug is problem solving. For many hardware developers, debug is a purpose. Finding a bug is a victory! Heck, debug can be flat out heroic. I’m sure we can all think back to colleagues that put in a few 80 hour, coffee fueled weeks, with managers peering over both shoulders, to fix an insidious string of bugs that threatened to further demolish a broken schedule and sabotage tape-out. W... » read more

Preparing For The IoT Data Tsunami
By Ann Mutschler - 29 Feb, 2016 - Comments: 0

Engineering teams are facing a flood of data that will be generated by the [getkc id="76" comment="Internet of Things"], both from the chip design side and from the infrastructure required to handle that data. There are several factors that make this problem particularly difficult to deal with. First, there is no single data type, which means data has to be translated somehow into a usable f... » read more

Racing To Design Chips Faster
By Ed Sperling - 25 Feb, 2016 - Comments: 6

A shift is underway to develop chips for more narrowly defined market segments, and in much smaller production runs. Rather than focusing on shrinking features and reducing cost per transistor by the billions of units, the emphasis behind this shift is less about scale and much more about optimization for specific markets and delivering those solutions more quickly. As automotive, consumer e... » read more

The Ultimate Shift Left
By Anupam Bakshi - 25 Feb, 2016 - Comments: 0

Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several semiconductor development teams, especially those in Fortune 500 companies, who do not have time to change their design process. They often cite various reasons such as: • Too busy with the current project. • What we have is working, so... » read more

Education And Communication
By Frank Schirrmeister - 25 Feb, 2016 - Comments: 0

With the System Development Suite introduced back in 2011, it is worthwhile to review how the adoption of the connected verification engines has progressed. It turns out that only part of the issues to be solved are purely technical. Communication across different technology areas is key, and with that, education of a new breed of engineer may become a key issue going forward. As a son of a ... » read more

UVM: It’s Organized And Systematic
By Henry Chan - 25 Feb, 2016 - Comments: 0

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamental... » read more

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