Formal Verification Applied To The Renesas MCU Design Platform Using OneSpin Tools


An effective measure of verification progress, together with guidance towards design areas remaining untested, requires a precise view of the test coverage achieved. To risk signing off the verification process without understanding the quality of testing raises the specter of post-production device bugs. OneSpin Solution’s patented Quantify technology employs Observation Coverage, which eval... » read more

Are Simulation’s Days Numbered?


Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro... » read more

RTL Done And Other Bogus Development Milestones


My definition of progress has changed over the years. I don’t think about it much anymore but it was obvious in a talk I gave a few weeks ago to a diverse group of hardware developers. Part of that talk centered around how we define progress in design and verification. This is a normal thing for me; I was speaking to slides I’d used several times before and the message was no different than... » read more

It’s Transition Time


For the past couple of years we've been hearing about the coming onslaught of the IoT, difficulties in scaling device features and a shift left that will redefine verification, debug and software prototyping. It's all happening. Taken individually, these are noteworthy changes. Taken as a whole, they represent a massive repositioning of the semiconductor industry, from architectural explorat... » read more

A Formal Transformation


A very important change is underway in functional verification. In the past, this was an esoteric technology and one that was difficult to deploy. It was relegated to tough problems late in the verification cycle, and it was difficult to justify the ROI unless the technology actually did find some problems. But all of that has changed. Formal verification companies started to use the technology... » read more

The Making Of A System Architect


I mentor young people from the University of Illinois at Urbana-Champaign, where I got my MSEE. When I talk to them, they tell me they’re applying for chip architecture jobs. But when they graduate with their computer science degrees they all get channeled into verification jobs. Why verification jobs rather than architecture jobs? Because they don’t have a feel for the full architecture. T... » read more

An Unsustainable Divide


One of the great things about attending DVCon, or any other conference for that matter, is the networking. You get to see so many people who are eager to learn, to talk and to share ideas. When this happens, you tend to hear a lot of statements that have to rattle around in your mind for a while before you can start to make sense of them and see if any coherent themes emerge. By themes, I am... » read more

Are Simulation’s Days Numbered?


In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

How Do Design And Verification Change In The IoT Age?


Where is the Internet of Things (IoT) on the hype curve? Are expectations too high, or is it really the next big thing? My recent trip to the Design Automation and Test Conference (DATE) in Dresden, Germany, did not give all the answers, but it definitely did shed some light for me on this topic. A very enthusiastic taxi driver took me back 25 years to the Nov. 9, 1989, the time when the Ber... » read more

Reducing Verification Risk With Formal-Based Observation Coverage


An effective measure of verification progress, together with guidance towards design areas remaining untested, requires a precise view of the test coverage achieved. To risk signing off the verification process without understanding the quality of testing raises the specter of post-production device bugs. OneSpin Solution’s patented Quantify technology employs Observation Coverage, which eval... » read more

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