tag: VHDL

Sigasi: Cleaner VHDL And SystemVerilog
By Ed Sperling - 30 Jan, 2017 - Comments: 0

Hardware engineers always have looked at software tools and methodologies with a certain degree of envy. While the hardware side has embraced the discipline necessary to get products right prior to release, in large part because it's too expensive to fix an error in hardware, the tools and languages are generally clunkier and the methodologies are much more rigid. Like software, they have to in... » read more

FPGA VHDL Verification
By Aldec - 22 Dec, 2016 - Comments: 0

By Espen Tallaksen This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost. All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good to... » read more

Embedded FPGAs Going Mainstream?
By Brian Bailey - 27 Oct, 2016 - Comments: 0

Systems on chip have been made with many processing variants ranging from general-purpose CPUs to DSPs, GPUs, and custom processors that are highly optimized for certain tasks. When none of these options provide the necessary performance or consumes too much power, custom hardware takes over. But there is one type of processing element that has rarely been used in a major SoC— the [gettech id... » read more

What’s Next For UVM?
By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 09 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

Software Driving More Hardware Designs
By Ed Sperling - 27 Aug, 2015 - Comments: 2

The influence of software engineers is growing inside of chip and systems companies, reversing a decades-old trend of matching the software to the fastest or most power-efficient hardware and raising as-yet unanswered questions about what will change in SoC design. The shift is particularly evident in chips developed for high-volume markets such as mobile phones and tablets. It's also happen... » read more

Design By Architect Or Committee?
By Brian Bailey - 26 Mar, 2015 - Comments: 5

Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

FPGA Design And Verification in Mechatronic Applications
By Various Writers - 23 Aug, 2012 - Comments: 0

The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can requirements be expressed for a system that, while it contains digital elements, is fundamentally non-digital? Fortunately an executable HDL exists that extends the capabilities of the digital VHDL languag... » read more

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