How to speed up the implementation of a hierarchical test solution.
Arm and Mentor have jointly developed a reference flow for a hierarchical DFT and ATPG implementation with Tessent for any Arm subsystem based on Cortex A-series IP. The reference flow, described in this paper, provides documentation, seamless interfaces, and scripts that accelerate the implementation of a hierarchical test solution. Arm and Mentor are dedicated to enabling customer success, regardless of their level of experience implementing hierarchical ATPG on Arm cores.
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