The Search For The Next Transistor

In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond.

The industry has been exploring a number of next-generation transistor candidates, but suddenly, a few technologies are emerging from the crowded pack. At 7nm, for example, the leading contender is the high-mobility finFET, which makes use of III-V materials in the channels to boost the mobilities.

Then, at 5nm, two technologies—gate-all-around field-effect transistor and tunnel field-effect transistor (TFET)—are taking a narrow lead. Considered the ultimate CMOS device in terms of electrostatics, gate-all-around is a device in which a gate is placed on all four sides of the channel. In contrast, TFETs are steep sub-threshold slope transistors aimed at low-power applications.

The race is far from over, however. There is still a long way to go before chipmakers reach a consensus on the following and complex next-generation options: III-V finFETs; gate-all-around FETs; quantum-well finFETs; silicon nanowires; SOI finFETs; and TFETs. In addition, the other path is to go with a vertical chip architecture such as a 2.5D/3D stacked die and monolithic 3D.

Chipmakers likely will need to develop more than one type of architecture, as there is no single technology that will be ideal for all future applications. “There’s not going to be a single answer,” said Michael Mayberry, corporate vice president of the Technology and Manufacturing Group and director of components research at Intel. “There are many different answers. They will be targeted for different market segments.”

Still, Intel, TSMC and others appear to have one technology slightly ahead of the pack—gate-all-around. “We are working on it,” Mayberry said. “It’s on everyone’s roadmap.”

Intel also has a keen interest in TFET. Others have different opinions. The eventual winners and losers will be determined by cost, manufacturability and functionality. For example, in principal, the best transistor is one where the gate is wrapped around a carbon nanotube, Mayberry said. “We don’t know how to make that yet,” he said. “So, it’s not the one with the best power point. It’s the one you can put into manufacturing.”

The other question is whether the industry will maintain the two-year or so process technology cadence. As more economic factors come into play, the industry will likely move to the next process node much slower and may even prolong the nodes.

Extending finFETs
In 2014, Intel is expected to ramp up its second-generation finFET technology based on a 14nm process. Also this year, GlobalFoundries, TSMC and Samsung separately plan to ship their first-generation finFETs built around a 14nm-class technology.

Companies are also separately developing their 10nm finFET technologies, but the question is how far can the industry extend finFETs? For finFETs, the gate starts losing control over the channel from the 10nm to the 7nm node, said An Steegen, senior vice president of process technology at Imec. “The ideal and the furthest we can push a single finFET technology is down to a 5nm fin width and a 10nm gate length,” Steegen said.

So at 7nm, the industry must consider a new option. Based on the roadmaps from various entities, and insights from industry executives, the leading contender is the high-mobility or III-V finFET at 7nm. “From what we’re seeing, you will likely get an intercept of the III-Vs around the 7nm node,” said Bradley Howard, vice president of the Etch Advanced Technology unit at Applied Materials.

The electron mobilities for today’s silicon-based finFETs degrade at 7nm. Germanium (Ge) and III-V materials have higher electron transport capabilities, allowing for faster switching speeds. The first III-V finFETs will likely consist of Ge in the PFET, according to experts. Then, the next-generation III-V finFETs may consist of Ge for PFET and indium gallium arsenide (InGaAs) for NFET, experts added.

High-mobility finFETs face several challenges, including the ability to integrate the different materials and structures. To help solve part of the problem, the industry is working on a silicon fin replacement process. “It depends on who you talk to, but (the III-V finFETs) will likely be made using a replacement fin technology,” Howard said. “Basically, what you are doing is replacing the fins. You take a silicon fin and you have an oxide around it. You basically empty out the silicon and replace with III-V.”

Then, at 5nm, the industry could extend the high-mobility finFET. Another option is to develop a quantum well finFET, which, in many respects, is a next-generation III-V finFET. In quantum well finFETs, a well is built in the device to confine the carriers. “Quantum wells are interesting from an academic standpoint,” Howard said.

“Below 7nm, the structure of a finFET becomes somewhat dicey,” Howard said. “That’s where you will see gate-all-around structures for potential devices. And that’s what will carry us beyond the 7nm node for a couple of generations.”

What is gate-all-around?
As the fin width in a finFET approaches 5nm, channel width variations could cause undesirable VT variability and mobility loss, according to IBM. One promising option, gate-all-around FETs, could circumvent the problem. Gate-all-around FET is a multi-gate structure, in which a gate is placed on four sides of a channel. “It’s basically a silicon nanowire with a gate going around it,” Howard said. “That becomes your transistor. It looks different, but you have a source, drain and a gate.”

An Chen, senior member of the technical staff at GlobalFoundries, said there are some advantages and disadvantages with gate-all-around FETs. “I think that looks very promising,” Chen said. “Gate-all-around has better electrostatics, but there are some fabrication issues.”

Gate-all-around FETs could be difficult and expensive to make. In just one example of the complexities, IBM recently described a gate-all-around silicon nanowire MOSFET, which achieved a nanowire pitch of 30nm and a scaled gate pitch of 60nm. The device had an effective nanowire dimension of 12.8nm.

In IBM’s gate-all-around fabrication process, two landing pads are formed on a substrate. The nanowires are formed and suspended horizontally on the landing pads. Then, vertical gates are patterned over the suspended nanowires. In doing so, multiple gates are formed over a common suspended region.

A spacer is formed. Then, the silicon nanowires are cut outside the gate region, according to IBM. In-situ doped silicon epitaxy is then grown from the exposed cross sections of the silicon nanowires at the edge of the spacer, according to IBM. Conventional self-aligned, nickel-based silicide contacts and copper interconnects were used to complete the device.

There are other versions of gate-all-around. For example, the National University of Singapore, Soitec and Leti recently described a Ge gate-all-around nanowire PFET. With a wire width of 3.5nm, the device was integrated with a phase change material, Ge2Sb2Te5 (GST), as a liner stressor, thereby boosting the mobility.

Intel, meanwhile, is working on a different gate-all-around structure. “In this case, it’s a silicon channel device,” said Intel’s Mayberry. “It’s about 6nm in diameter. We can make something smaller than that. This is made up with lots of different types of materials, which are stacked up with atomic precision and in a 3D arrangement. It’s pretty hard to do over a very large volume. It’s an unsolved problem, but we are working on that.”

Other options
Gate-all-around is not the only option on the table. “Our work also finds that quantum well finFETs can also have equivalent electrostatic advantages,” said Aaron Thean, director of the logic program at Imec. “Basically, quantum well is an isolation scheme. Quantum wells are used to keep carriers where they are supposed be and keep out the leakage.”

Recently, Imec, GlobalFoundries and Samsung demonstrated a quantum well finFET. Using a fin replacement process, the companies demonstrated a strained, Ge-based channel PFET. “You can make a quantum well device on III-V. You can make a quantum well device out of germanium. You can make a quantum well device out of silicon and silicon germanium,” he said.

Another distant form of a quantum well device is FDSOI, where the silicon acts as a well and the oxide serves as the barrier. “My opinion is that 7nm will still be a Si and SiGe finFET on SOI with built-in strain,” said Ali Khakifirooz, an advisory engineer and a scientist at IBM.

IBM also is working on another technology, dubbed “aggressively scaled strained-silicon directly-on-insulator (SSDOI) finFETs. In this technology, the wafer is a strained-silicon layer bonded to oxide. FDSOI technology is supposedly easier to manufacture than bulk, but the substrates are more expensive and the infrastructure is still immature.

In fact, each next-generation transistor candidate has various trade-offs, making the choices complex. “I personally have great concern about the usefulness of III-V as a replacement for the silicon in the MOSFET channel,” Khakifirooz said. “Gate-all-around has better electrostatics, as compared to finFET. Gate-all-around can be scaled to shorter Lg, but there are a few challenges. For example, if gate-all-around is made on a bulk substrate, it needs some tricks to isolate the gate from the substrate without a capacitance penalty.”

There are other, and perhaps more important, issues to consider. “The fact that everyone is working on gate-all-around is one thing,” he said. “Whether we see it in production at 7nm or 5nm is something else. You also may or may not need gate-all-around. We need the answer to that question from the circuit designers first and then from the technologists.”