Week In Review: Design, Low Power

RISC-V
Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in various internal embedded designs. The SweRV ISS offers full test bench support for RISC-V cores and was used to simulate and validate the SweRV Core. Finally, OmniXtend is an approach to providing cache coherent memory over an Ethernet fabric. Its memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components.

Codasip uncorked the latest version of its tool suite for development and verification of RISC-V processors. The tools allow designers to write a high-level description of a processor in the architecture description language CodAL and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK. The methodology uses an Instruction Accurate processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

Codasip also announced its Bk7 processor, a RISC-V core optimized for Linux and real-time performance. Bk7 is a 64-bit machine featuring a balanced 7-stage pipeline with branch prediction, optional full MMU with virtual addressing support, and support for RISC-V standard extensions and industry-standard external interfaces. Plus, Codasip recently raised $10 million in Series A funding led by private equity firms Ventech Capital, Shenzhen Capital Group, Paua Ventures, and strategic investor Western Digital. The funds will be used to grow its global sales and support team and expand product development efforts.

Microsemi announced a new architecture for SoC FPGAs that combines its low power mid-range PolarFire FPGA family and a microprocessor subsystem based on RISC-V. The architecture, developed with SiFive, provides real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent CPU cluster and features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory.

Andes Technology uncorked Andes Custom Extension (ACE) for its recently-announced line of RISC-V cores, allowing embedded designers to add customized instructions to Andes V5 CPU cores. The ACE design environment uses a description file that describes instruction input/output interfaces and instruction semantics in C and a concise Verilog file implementing the RTL logic based on the given interfaces to generate the extended CPU and software toolchains. It offloads all housekeeping RTL design tasks such as opcode selection, instruction decoding, operand mapping, input operand accesses, dependence checking and result gathering and requires no expertise in processor pipeline design.

Valtrix and Imperas teamed up to integrate Valtrix’s STING bare-metal software tool for verification of SoC implementations with Imperas’ free RISC-V instruction set simulator, riscvOVPsim. The integration allows for configuration of virtual platforms as a verification reference as well as extending the RISC-V envelope model with custom instructions. Additionally, Esperanto Technologies will use Valtrix’s STING for verification of its RISC-V-based 7nm AI SoC.

Tools & IP
Achronix launched its latest eFPGA IP, Speedcore Gen4. The architecture adds a new Machine Learning Processor (MLP) block, a flexible compute engine tightly coupled with embedded memories and high performance per watt aimed at AI/ML acceleration. The MLPs support multiple precision fixed point and floating point formats, and the Gen4 eFPGA IP implements 6×6 multipliers in 11 LUTs and can operate at 1 GHz. Architecture changes include doubling the size of the ALUs, doubling the registers per LUT, support for 7-bit functions and some 8-bit functions in a single level-of-logic delay, and dedicated high-speed connections for shift registers, improving overall performance 60% over the previous generation.

Imagination unveiled three new GPU families in its PowerVR Series9 lineup ranging from entry-level to high-end. All feature PVRIC4 visually lossless compression for reduced bandwidth and memory footprint. The Series9XEP is based on the Rogue architecture, features timing improvements for higher core clock speeds, and targets products such as set-top boxes, DTVs, low-cost mobile devices. The Series9XMP, also based on the Rogue architecture, provides increased compute density and targets mid-range mobile devices, set-top boxes and DTVs. The Series9XTP, based on the Furian architecture, provides up to a 50% fps/mm2 density increase with extensive PPA optimization and more options for ALU width and targets premium mobile devices and high-end infotainment.

Imagination also debuted its latest neural network accelerator architecture, PowerVR Series3NX. A single Series3NX core scales from 0.6 to 10 TOPS, while multicore implementations can scale beyond 160 TOPS. It provides a 40% boost in performance compared to the previous generation. A flexible IP configuration is also available. It is targeted to embedded markets such as automotive, mobile, smart surveillance and IoT edge devices.

RF IC design services company CoreHW is making available its library of over 200 IPs on a variety of foundries and process nodes. IP is targeted at imaging, Bluetooth, IoT, and WiFi.

Plunify added per-minute pricing, starting at $0.007, to its cloud-based program for FPGA design. The model includes servers, networking, storage, and tool licenses. An optional pre-paid mechanism allows for control of expenditures.

Rambus inked a deal with Micron, which will use Rambus’ CryptoManager in its Authenta secure memory product line for IoT devices. It will allow Micron to securely provision cryptographic information at any point in the extended manufacturing supply chain and throughout the IoT device lifecycle.

Numbers
Synopsys released fourth quarter financial results with revenue of $795.1 million, up 14.1% from the fourth quarter of 2017. On a GAAP basis, earnings per share for Q4 2018 were $1.66, compared to a loss per share of $0.80 in Q4 2017. Non-GAAP income was $0.78 per share, up 13% from $0.69 per share in the same quarter last year. For the whole year, Synopsys saw revenue of $3.121 billion, up 14.5% from FY2017. On a GAAP basis, income was $2.82 per share for the fiscal year, up from $0.88 per share in 2017, while non-GAAP income was $3.91 per share, up 14.3% from $3.42 per share last year. “Our objective is to drive annual double-digit non-GAAP earnings per share growth, through a mix of continued solid revenue growth and expansion of non-GAAP operating margins to the high 20s over time, with a goal of ~26% in 2021,” said chairman and co-CEO Aart de Geus.