Analog Fault Simulation Challenges And Solutions

Part 1: Why analog circuit test time has not benefited from improvements in test and what to do about it.


The test time for digital circuit blocks in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression. These technologies have greatly reduced the number of test vectors applied by automatic test equipment (ATE) while maximizing the coverage of a wide range of defect types.

But for analog circuits, test time has hardly decreased at all. For mixed-signal ICs, test time for the analog portion often dominates total test time. Yet, data for automotive ICs shows that defects in analog circuitry dominate test escapes. A new approach is needed to improve test coverage and defect tolerance. That solution is Tessent DefectSim for transistor-level fault simulation for analog, mixed-signal, and non-scan digital circuits. Learn more about it in this introductory white paper. To read more, click here.