Fallout From Scaling

There are an increasing number of options to deal with the device scaling issues. All of them present challenges.


By Ed Sperling & Ann Steffora Mutschler

Semiconductor scaling is becoming much more difficult and expensive at each new node, creating sharp divisions about what path to take next for which markets and applications. What used to be confined to one or two clear choices is now turning into a menu of items and possibilities, often with no clear guarantees for a successful outcome.

Views about the future of Moore’s Law tend to fall into three main camps—alive, dead, or slowing—and while each of them is based upon different interpretations of similar data, those views vary greatly by market, by company, and sometimes from one chip to the next even within the same company. The different interpretations are largely responsible for a confusing array of options, such as whether to push to the next node with whatever finFET technology is available, whether to utilize advanced packaging techniques such as 2.5D or fan-outs, or whether to use different substrate materials such as FD-SOI. On top of that there are more options to stay at established process nodes using updated process technology, as well as to do designs differently with asynchronous approaches.

The increase in possible approaches has massive implications for the entire semiconductor ecosystem. At the foundry level, this has turned into a multi-directional challenge that requires some very large investments in equipment, expertise, process R&D and packaging.

“It’s a high-stakes game,” said Kelvin Low, senior director of foundry marketing at Samsung. “There are individual offerings at 14, 10 and 7nm that will be suitable for certain solutions. There is still pressure to go down the technology curve. Our 14nm is in mass production and at 10nm we art targeting to go into mass production by the end of the year. But 10nm uses more complex lithography. Triple and double patterning will be employed.”

The investment required on all sides is huge, and the payback subsequently needs to be proportionate, which in increasingly fractured markets may be impossible for most chipmakers to achieve. Unlike the mature smart phone, PC and enterprise server markets, there is no single market segment at this time with enough clear growth potential to provide that scale. Even though the increase in automotive SoCs is significant, it’s nothing like an applications processor for a high-end smart phone that can be sold into billions of devices.

“The investment in new process technology is very high,” said Subramani Kengeri, vice president of global design solutions at GlobalFoundries. “You need a $20 billion to $30 billion market to justify that investment and break even. For fabless companies, it may cost $500 million to move to a new process.”

All of the big foundries say they are committed to device scaling to at least 7nm, and Intel has road map that goes at least a node beyond that. But there also are growing problems at each new node, including some new ones that were never design considerations in the past.

“You now need to consider chip, package, board and system in the design,” said Ravi Ravikumar, senior marketing manager at Ansys. “It’s not just about the chip anymore. The amount of heat these chips are generating is having an impact on the solder joints on a board. You also need to add more vias into these chips. That adds more stress, too. Over time, the joints are weakened and they will break.”

Another challenge for the system architect at advanced nodes is just having all of the pieces available to do a design. “Chasing technology nodes does come with additional considerations,” said Samsung’s Low. “It’s one thing to have a 10nm process. It’s another to have a high-speed SerDes for that node when you need it.”

New materials for new markets
Rather than approach the scaling problem head-on, Samsung, GlobalFoundries, STMicroelectronics, and Leti are backing fully depleted silicon on insulator as a lower-cost alternative. While this was originally touted as an alternative to double and triple patterning and finFETs, the new emphasis is on cost-sensitive IoT applications such as the connected home or wearable electronics.

Both FD-SOI and finFETs use fully depleted silicon, but FD-SOI adds body biasing to improve energy efficiency. Samsung offers a 28nm version of FD-SOI. GlobalFoundries has developed a 22nm version of the process that it claims is roughly competitive on performance with finFETs, as well. It’s too early to tell how this technology will fare in the market, but investments here are significant, as well.

There are two big questions that remain for FD-SOI. One is how aggressive the roadmap will be for this technology. There is also research underway into finFET on insulator, according to industry sources.

In addition, GlobalFoundries is considering a 10nm planar version of FD-SOI, but timing is unknown. The second factor that is unknown is how useful EUV lithography will become and when. While EUV is in use today, there are still issues with uptime and throughput. If a 16/14nm finFET-based chip can be single patterned with EUV at a reasonable cost, it may change the economics of moving to that node. But so far, that doesn’t appear promising considering EUV has missed at least two process nodes.

Packaging options
Alongside of those two choices are advanced packaging options, which are ramping quickly in the marketplace. Foundries are clear that they intend to support 2.5D and fan-outs along with all process geometries, because packages can contain chips that were developed using different processes and even different materials. So it’s possible to put an FD-SOI chip developed at 22nm in the same package as a 130nm analog chip and a 40nm memory. Those packages can contain finFETs, as well.

This alleviates some of the issues of having all of the pieces ready on time and questions about whether roadmaps for different processes and materials are accurate enough.

“We finally see 2.5D gaining real traction in the marketplace as a way to leverage multiple technologies,” said Mike Gianfagna, vice president of marketing at eSilicon. ” One of the primary drivers today is high-bandwidth memory (HBM). With HBM, you can add substantial amounts of memory as separate silicon and interface them to your chip via high speed HBM interfaces on a silicon substrate. The application is typically high-performance computing or networking – two areas that are seeing growth as part of the IoT trend.” He noted that the eSilicon is working on several 2.5D projects in multiple areas.

The foundries and OSATs have seen this trend coming for some time and have been developing interposers and ironing out problems with microbumps for at least the past five to seven years. Samsung Foundry has been revving up its offerings in this area with a new version of high-bandwidth memory (HBM2), which it rolled out earlier this month. Its Foundry Division also has been adding expertise and experience in 2.5D and 3D packaging. Meanwhile, TSMC has been touting its expertise in fan-outs (InFo, or integrated fan-out) and 2.5D (CoWos, or chips on wafer on substrate). And GlobalFoundries has been talking about ways to use its 14nm finFET technology as a logic platform inside of 2.5D packages.

“You can mix and match and get the best of everything,” said GlobalFoundries’ Kengeri. “So you can take a low-cost, low-power process and you can mix and match it with other processes to get the best of everything. With 2.5D, you can take out the MEMS and sensors and put them on a separate chip.”

Still, there are issues that need to be smoothed out over time. The issue of known good die has not changed, although it is better using 2.5D or fan-out packaging than 3D-IC, where heat and the handling of thinner die can be problematic. There also are issues of inventory management—having enough of everything on hand to meet demand—as well as yield accountability.

What’s particularly attractive about advanced packaging is that it allows companies to combine new options at older nodes with the most advanced nodes. eSilicon’s Gianfagna said 28nm will likely be around for a long time because it can use planar bulk silicon without double patterning, even if that ultimately is paired with other more advanced technology in the same package.

“The foundry options for this node, well-developed IP ecosystem and significant cost increase at lower nodes is driving this,” Gianfagna said. “There is a lot of creativity around 28nm designs.”

Impact on design
The fallout of all of these choices isn’t necessarily bad, though. In fact, it can be quite lucrative for tools vendors, particularly for simulation, emulation, verification and prototyping. Mixing and matching of possibilities can extend to new customers, who have done most of the possible tradeoffs in the past using spreadsheets.

Frank Schirrmeister, senior group director, product management in the System & Verification Group at Cadence, observed  there currently is a bifurcation, if not tri-furcation, of markets. At the very high end are the applications processors and server chips. “There are power questions, there’s a concern about cost—such as discussion around the cost going up in the very low nodes—but there’s still a reason for doing it for the very complex chips,” he said, noting that large capacities are particularly valuable here, particularly for emulation. “There’s a lot of used capacity in the very complex designs. Given the scaling, and given that what it takes to design such a chip, it becomes a very hotly contested market, and you want to get a lot of capacity in there.”

Capacity is a growing concern everywhere. “With all the variables this is becoming a multi-dimensional equation,” said Ansys’ Ravikumar. “You have to use per-bump, not the lumped modeling of parasitics and analyze power integrity taking thermal into account. This also requires a chip thermal model.”

This makes for good business, and it’s reflected in the big investments that EDA vendors have been making recently in tools, and the increased performance of those tools with an emphasis on multiprocessing. Even markets that until recently were not considered an opportunity are now being viewed differently.

“In the IoT, you actually have a scaling in volume of lots of chips, but they are very, very small,” said Cadence’s Schirrmeister. “The verification challenge becomes different because I now have to look into analog/mixed-signal. I want to make sure that it’s connected to Bluetooth correctly, for example. The assembly for this has to be really, really fast. There, scalability means how I can make sure that I can integrate my IP really in a pushbutton way. Scaling of verification there really becomes an issue of how fast can I spin the next revision of a verification task to run on any of the engines I have available—simulation, emulation or FPGA prototyping.”

Ravikumar agrees. “With analog, you now have power-noise issues. Voltage levels are going lower, but noise margins are very low.”

Behind all of this is another cross current, namely what needs to be in analog and what needs to be in digital. As long as there was only one direction of choice, shrinking features, the push was on to digitize everything. But if analog and digital can be on separate chips in a package, each using their optimum process technology, that can have a significant impact on a number of choices that span from architecture to tools.

Joe Hupcey, Questa product marketing manager at Mentor Graphics, said that when engineering team input low power design techniques, they insert isolation cells, buffers and other devices to implement low power structures. That can wreak havoc on clock domain crossings. “Once you introduce low power, you need to re-run CDC because that can introduce issues that can kill your chip,” he said. “By extension, there is rising interest in a gate-level CDC, where now you have gate-level models, and it’s the fully realized circuit. It’s all gate level. It has the timing back annotated for all of those cells, and then you run a CDC analysis on that. As things are, after that post implementation phase, post synthesis, other things can be optimized away or crop up or be introduced for whatever reason and it can create an asynchronous path that you didn’t think was there before. I can imagine in the future where the cells have these interdependencies now and somehow that’s modeled by some smart person, and that is back annotated to digital simulation that have to be analyzed, analogous to power aware CDC.”

That really begs the question of how long pure digital modeling can hold up, he said. “My gut feeling is there’s a good decade where my colleagues in the physical space will be clever enough to keep those nasty real world effects buffered from us and we can still pretend everything is digital.”

All of these choices add another element, as well. Collaboration across the ecosystem used to be relatively well defined. That’s no longer the case, and companies that rarely or never talked are now exploring possible relationships.

Anupam Bakshi, CEO of Agnisys, said his company is working with a major chip company on a new tool that enables multiple teams to collaborate on a specification and do the work together so that the validation tests can be scaled.

The number of options and possibilities is only going to grow. That will certainly add disruptions into a business that had been refining a roadmap based upon shrinking features since the introduction of Moore’s Law a half-century ago. Add in factors such as the Internet of Everything, new packaging solutions, global competition, and a new crop of engineers with a background in software and computer science and changes are almost certain to be profound industry-shaking.

Chipmakers have been preparing for these changes through a series of acquisitions and spinoffs. Packaging houses and foundries have been working on alternatives to simply shrinking features. And tools vendors have been developing new tools and augmenting existing tools to address all of these shifts. But how the industry ultimately changes, and how quickly that happens, remains a big question mark that has everyone second-guessing what comes next—and leaving chipmakers facing a myriad of choices, none of which is fully baked.