One-On-One: Dave Hemker

Lam Research’s CTO looks at inflections in transistors and memory, lithography issues, an increased focus on cost, and what will change at 7nm and 5nm.

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Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Dave Hemker, senior vice president and chief technology officer at Lam Research.

SE: On the technology front, the IC industry is undergoing some new and dramatic changes. What are some of those changes?

Hemker: We focus on what we call the inflections. If you walk through the inflections, you have finFETs. For one customer, they are in their second-generation of finFETs. Others are working on a rollout of their first iterations. So we are in a period of taking them to the next level. In memory, you have the transition to 3D. For 3D NAND, there are products that have been shipped, at least from one of our customers. The question is how does it move to where it’s more pervasive across the customer base.

SE: Any other inflection points?

Hemker: Another inflection is taking place in patterning or lithography. EUV isn’t going to be available in any meaningful way before 7nm. Multiple patterning has been going on for awhile. Now, you are seeing that becoming more pervasive. You are seeing a move from double-, to triple-, to quad-patterning. From our perspective, we also are seeing much more atomic layer deposition for the spacers in patterning. Obviously, etch is also important. You have multiple passes through the etcher to do multiple patterning.

SE: How do these inflections impact capital spending?

Hemker: One of the overriding themes that Martin Anstice, our president and CEO, has been saying is that we’re seeing a lot of rational decision making in the market. If you look at what has driven cycles in the past, there have been a lot of factors. There has been a component of less rational decision-making. Today, everything we are seeing is that in all of the spaces—logic, foundry and memory—it’s pretty rational. Actually, that’s always a good thing. It’s a healthy thing. A lot of people are attributing that to one of the by-products, or at least part of the by-product, of consolidation in the customer base.

SE: Let’s go back to finFETs. Isn’t finFET production from the foundries taking longer than expected?

Hemker: We expect the 14nm/16nm finFET ramp from the foundries to happen this year. Go back and look at any other inflection in history. Look at high-k/metal gate, for example. I am looking at it from a bigger picture. This is always what we go through to some varying degree when we go through a major technology inflection.

SE: Do you have any concerns about the yield ramp with finFETs?

Hemker: Individual companies are going to have varying rates in which they work through the yield issues. But I don’t see anything that’s disturbing to the point where finFETs are not going to happen. You will see it happen this year. Any variation will be short term.

SE: What about 3D NAND? Is it taking longer than expected?

Hemker: It’s not a matter of if, but when 3D NAND will happen. Any variation on the ramp is really due to how the manufacturer views the economics. In 2015, everybody is clearly increasing the amount of 3D investment and effort. And then, the actual ramp, whether it’s this year or next year, is driven by the situation of a given company. 2015 will be the year where the development programs and pilot lines will expand.

SE: What are the challenges in 3D NAND?

Hemker: In 3D NAND, there are some enormous challenges in terms of being able to accurately put down the alternating stacks, which build up the memory device. Then, you have to drill a hole through them. You have to make contacts. You have to backfill them with a conductor, which is tungsten. You have to be aware of the subtle changes when you are etching oxide and nitride. And you need to have perfectly vertical profiles and they need to maintain the CD.

SE: What about etch?

Hemker: Obviously with etch, you have to drill the holes down through the entire stack and then make the contacts on the edge. People call this staircase etch. There is a slit etch as well, which is pretty challenging.

SE: Will advanced 2.5D/3D stacked die ever happen?

Hemker: The capabilities are fully there. It has been demonstrated. And so now it becomes an economic question. You are seeing niches in 2.5D and even 3D, where there are performance benefits. A lot of people thought that 2.5D/3D was an easier way to stay on Moore’s Law. Right now, though, the economics for 2.5D/3D is really where you need performance. The Hybrid Memory Cube is a good example. You can get much higher memory bandwidth by stacking the chips.

SE: What could speed up the adoption of 2.5D/3D?

Hemker: If you had standards in the area, it would help. That’s not all that is needed. But if I could go out buy a memory from one manufacturer, and then go to a foundry and have my own logic designed, then I could take those two independent chips and mount them vertically. But right now, you have to design it from the beginning. There is still a lot of design, with the fact that designers know that an interposer will be used sometime in the future. It’s not off-the-shelf kind of stuff.

SE: Let’s go back to logic. What will 7nm look like?

Hemker: Every time we are working on a new node, we want to make it as incremental as possible. People are not going out and saying: ‘I hope I can go out and change the transistor.’ So at 7nm, if you look at the transistor, it might be a scaled 10nm finFET. You will see germanium playing a bigger role, whether its silicon-germanium or germanium. That part must be worked out. It’s less likely you will see III-V in there, because I don’t think it’s needed at that node. In the backend, there will be some challenges just to continue that scaling. That may end up being more levels of metal. Or you may see more aggressive scaling in terms of the barrier layer seed. But I don’t anticipate any earth shattering changes, like when we went from planar to 3D finFET.

SE: We may see a next-generation transistor type at 5nm, right?

Hemker: The evolution of the transistor is some sort of nanowire. There is a horizontal nanowire. Some people call it the lateral nanowire. This could potentially be the evolution of the current finFET.

SE: Can you describe a nanowire FET?

Hemker: Basically, you chop up the fin up into multiple segments and wrap the gate around it. That’s one path. People are also working on vertical nanowires, which is a little more of a radical departure.

SE: What’s your take on EUV right now?

Hemker: It’s just a super-hard engineering problem. I am not surprised at the pace it’s taking. I am also not surprised when EUV makes progress. But it’s by no means a slam-dunk. There are still a lot of challenges. It’s not only the source. There are also pellicle issues and inspection.

SE: If needed, can the industry do octuple patterning?

Hemker: Technically, it’s been shown you can do it. Economically, does that make sense for every device? Probably not. The one thing that is happening is that as more multi-patterning equipment gets shipped, and chips get made with it, the learning continues to increase. And the longer this goes, multiple patterning is maybe not quite as expensive as we originally thought. It actually becomes more productive. Again, is that going to be the complete solution? Probably not.

SE: What’s the progress of atomic layer etch?

Hemker: It’s good. We’ve got a number of engagements, including most of the major players, who are looking at high-aspect ratio kind of etches. Some of the more recent ones are looking at memory applications. Internally, we call it an N+2. So it’s a couple of generations out. That’s exactly where you expect it to be in terms of a new technology. In the past year and continuing into 2015, we want to get this new capability into the R&D groups of all of our customers. So in turn, they can see it and find out what they can do with it. Atomic layer etch will be important, but it will take time to roll out.

SE: Intel says Moore’s Law isn’t slowing down. Any thoughts?

Hemker: I am encouraged by Intel’s current graph showing the reduced cost of the transistor. They have not seen any disaster or things going off the cliff. That’s the real the bottom line for them. Each generation has a lower cost transistor, which follows a certain curve. It’s getting more difficult and parts of it are more expensive. But clearly, they are getting enough value and they are finding ways of doing it economically.

SE: Chipmakers are developing finFETs, 3D NAND and stacked die. The industry is also working on EUV. Are there enough R&D dollars to do all of those things?

Hemker: At the top of the ecosystem, there is still enough money there. It’s just how we go about partnering to do the research and who is expected to fund what.

SE: What happened to 450mm?

Hemker: That was one of the issues with 450mm. That R&D model didn’t work. So it didn’t happen. It won’t happen until the economics make it work.

SE: So what gets funded and what doesn’t?

Hemker: If there is a particular need for a technology that has not been developed, there has to be enough of a demand for someone to do it. And that’s why you are seeing 3D NAND. That’s why we have finFETs. There is enough demand to warrant the R&D investment, up and down the whole ecosystem. This is not just the device guys, but also the equipment and materials suppliers as well.