How last year’s predictions for tools, design and manufacturing panned out over the past 12 months.
Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off.
Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made at this time last year to determine who got it right and who didn’t. All participants have the option to comment on their own predictions. Of 17 companies that made predictions, 7 of them chose to judge themselves.
Lucio Lanza, managing director for Lanza techVentures, reminded us that “the EDA tagline ‘Where Electronics Begins’ is no exaggeration.” He reminded us about how important innovation is within EDA. Michiel Ligthart, president and chief operating officer for Verific Design Automation, added that “no company wants to use the same solution as the next. As a result, the differentiation has moved down over the past few years to the design flow, where many companies are extending their design and verification flows with homegrown improvements.”
He responds saying “While it turned out to be true that semiconductor companies continue to pull design flow tools in-house, evident by the requests for SystemVerilog parsers we received, I was incorrect to assume we would see fewer startups. In fact, we hosted three at our booth at DAC — Austemper, Innergy and Tortuga Logic — and have been talking with several more over the past 10 months.”
2016 was most certainly a year when verification took center stage. One of the areas that has received a lot of attention Accellera’s Portable Stimulus Working Group (PSWG). “2016 will also be an exciting year as we welcome the first standard for a new verification methodology that could bring efficiency back into the verification process,” said Adnan Hamid, chief executive officer of Breker Verification Systems. “PSWG will release a standard defining a single abstract, graph-based specification that can be used to automatically generate test cases (stimulus, results, and Coverage) for multiple verification environments and platforms.”
Hamid sees additional trends within the industry that are driving this trend now. “The continued consolidation in the semiconductor space is being driven by cost reduction and the area in which the most savings can be made is in verification and validation. Companies are demanding that better methods are required that do not require re-writing and re-debugging tests at each level of integration. The ongoing move toward portable tests is an example of users demanding that verification solutions be portable ‘vertically’ from block to SoC, and ‘horizontally’ from simulation through emulation and FPGA prototyping to actual silicon in the lab.”
However, the prediction was that a standard would be released in 2016 and that did not happen. “Everyone in the standards group is working hard to get to a standard in the first half of 2017,” continues Hamid. “A lot of progress has been made and we are perhaps 80% to 90% convergent. More work is being done to get the right standard, rather than taking shortcuts with something that will have less usefulness to the end user.”
Tom Anderson, director of product management for the System & Verification Group at Cadence, adds that “I expected increasing momentum as I looked forward to 2016, and this was indeed the case. The PSWG has continued its effort and provided the industry with well-attended update tutorials at several major industry events, including DAC and the DVCon shows in Silicon Valley, Europe, and India. There is little doubt that portable stimulus is the ‘next big thing’ for functional verification.”
There are very good reasons for the delay in the standard. The first is that it has attracted more user attention that originally expected. The second is that “the users have made it very clear that they want the ability to leverage the power of C++ models in addition to the definition of a domain-specific language,” adds Hamid.
The notions of vertical and horizontal reuse and integration within verification are also having an impact on the areas of emulation and prototyping. “Cadence has been an advocate for a combination of virtual prototyping, simulation, formal, emulation and FPGA-based prototyping since 2011,” says Frank Schirrmeister, senior group director of product management for the System & Verification group of Cadence. “The integration between the verification engines, dynamic and static, has grown much stronger. Add to that the efforts in the PSWG to allow horizontal re-use of tests across those engines, and you arrive at much closer-connected flows.”
Schirrmeister adds that “vertical integration between abstraction levels has also become more mainstream in 2016, as well. Specifically for low power, activity data created from execution of RTL in emulation can be connected to power information extracted from .lib technology files. This allows the estimation of hardware-based power consumption in the context of software, using deep cycles over longer timeframes that are emulated. As to connections between RTL and TLM, 2016 saw further adoption of hybrid approaches, connecting, for example ARM Fast Models with emulation.
Marc Serughetti, director of business development for system level solutions at Synopsys, expected similar kinds of integration. “Prototyping has provided a solution to address such requirements, although traditionally the solutions have been disconnected, with each solution addressing a specific problem.” Serughetti responds, saying “Virtual Prototype, physical prototyping, and emulation are all bringing specific value along the development chain and provide a continuum of technology that overall accelerates the development for semiconductor companies. Some of these technologies (like virtual prototyping) also provide a path for semiconductor customers to accelerate their development.”
There are several factors pushing adoption of both emulation and prototyping. “We have seen a significant interest in more collaboration between semiconductor companies and Tier1/OEM when it comes to ensuring the performance of a chip is estimated earlier,” explains Serughetti. “Today there is more than can be done in this area, but clearly we are on a path where this collaboration is required. In general, the existing deployment activities as well as the overall market trends we see from the EDA companies are confirming that the prediction was right. The deployment of these technologies is an on-going process.”
There has been an increase in awareness about security issues during 2016. “One of the most complex challenges for designers will be to understand security options and implementations for connected devices and the market requirements for individual segments,” said Ron Lowman, strategic marketing manager for IoT within Synopsys. He responds, saying that “we have seen increased implementations of security hardware to secure IoT solutions. Embedded security information management solutions will dominate design discussions.”
Nobody predicted that anything would happen to the big three this year, as they have in previous years, but then nobody expected the pending acquisition of Mentor Graphics by Siemens. While the general population is still not quite sure what to make of this, including the long-term implications of this deal, it is a sign that the EDA industry is undergoing considerable change. That change is likely to continue, too. Synopsys is emphasizing software and security a lot more, and Mentor has been branching out into the systems space, embedded software and other areas.
Semiconductors, manufacturing and design
The manufacturing theme for 2016 was set by Aki Fujimura, CEO of D2S, who said, “Even though Moore’s Law makes everyone in the supply chain stay on their toes to keep up with the constant cycles of change, big discontinuities are rare. The industry tends to stick with what it knows. Like a big earthquake, after a few generations, incremental improvements on the status quo just can’t keep up any more. In semiconductor manufacturing, the big quake is coming soon.”
Fujimura still believes that “we are getting closer to the earthquake – but this is good. It will be drastically different. Some unpredictable things are likely to break, and there will be many new opportunities for any kind of business that participates in infrastructures. Discontinuities are bad for business because it creates some unnatural things.”
Several technologies are pushing that earthquake. “The push to be able to use EUV for the critical layers is around the corner for wafer manufacturing,” Fujimura said. “Other alternative solutions such as nanoimprint lithography (NIL), directed self-assembly (DSA), and e-beam direct write will see significant announcements in their progress on the long road toward adoption for high-volume manufacturing in 2016.”
Fujimura sticks with his predictions. “The perceptions about EUV and eBeam are on track with what we were predicting. multi-beam e-beam has not been slipping like some technologies. A significant number of people were saying that EUV would never happen. That has declined dramatically over the past two years. People now believe that it will happen. It is only a matter of time. Significant things are happening. The mask infrastructure support for EUV is getting increasing attention. That is what we expect to see when the earthquake is coming. Then the surrounding areas start to prepare for it.”
During 2016 the industry was getting more comfortable with finFETs and Graham Etchells, marketing director of AMS at Synopsys, was concerned about productivity of physical designers. “The complexity of new rules, restrictions such as fin placement, higher parasitics, metal track requirements and the high impact of layout dependent effects all degrade designer productivity.” Etchells believes that constraint-driven, fully automated placement and routing is not the answer. “Putting in constraints to get what you want is tedious and time consuming, and you never get what you really want anyway. Assisted automation is what’s required.”
Etchells responds, saying “productivity was indeed a major concern for customers when they made the move to finFET technologies. The impact became even more severe with the introduction of the 7nm node. Firsthand experience of dealing with these technologies and the restrictions they imposed drove Synopsys to further improve the visually-assisted tool flow. Refinements were needed in the symbolic editor and interactive routing technology coupled with new via and track planning features helped with productivity.”
Synopsys’ Lowman expected to see “increased integration of wireless IP into monolithic solutions, in particular Bluetooth Smart and other low-bandwidth solutions.” He now says that “Bluetooth 5 combined with LPWAN technologies, in particular NB-IoT, will drive connectivity solutions for smart cities, smart homes and buildings. The trend to integrate RF has been proven but many have been a bit delayed due to the upcoming introduction of Bluetooth 5. Designs have been reluctant to take risks of integration when new interoperable standards are being introduced. The released Bluetooth 5 spec will expedite the technology adoption of monolithic solutions and RF integrated into MCUs because it has broader appeal to satisfy additional applications including location services, smart home and beyond.”
Fujimura sums it up well: “2016 was a year with no real disappointments. Companies and technologies advanced in the way that was predicted. Even fringe technologies, such as nanoimprint or directed self-assembly, progressed as had been predicted. When you have such a new technology as multi-beam, some things tend to go wrong and there are slips in the schedule, but that is not what we have seen. In September, they announced that they were taking orders. That is surprising for any product person who is used to people not being able to meet their exact schedule projected three years ago.”
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Emulation’s Footprint Grows
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Why EUV Is So Difficult
One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing.
E-Beam Vs. Optical Inspection
Wafer inspection market sparks to life as existing equipment struggles at 10nm.