Exploring New Scaling Approaches


At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography 2017 conference, Semiconductor Engineering sat down to discuss semiconductor technology with Tsu-Jae King Liu, the TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley. More specifically, Liu discussed some of the new... » read more

The Materials Gap


When consolidation thinned the ranks of semiconductor foundries and equipment makers, materials companies figured things were about to get better. They haven't. There are a couple of reasons for this. First, semiconductors are now so complex and difficult to develop that a slew of innovations are required on all sides. Everyone is familiar with transistor structures, interconnects and lithog... » read more

Samsung Unveils Scaling, Packaging Roadmaps


Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise. The moves put [getentity id="22865" e_name="Samsung Foundry"] in direct competition with [get... » read more

Extending EUV Beyond 3nm


Jan van Schoot, senior principal architect at [getentity id="22935" comment="ASML"], sat down with Semiconductor Engineering to talk about how far EUV can be extended and where it is today. What follows are excerpts of that discussion. SE: High numerical aperture [gettech id="31045" comment="EUV"] has been in the works for some time as a way of extending EUV. How is this technology shaping... » read more

Biz Talk: ASICs


eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Power/Performance Bits: Oct. 11


Getting to 1nm Researchers at the Lawrence Berkeley National Laboratory, UC Berkeley, University of Texas at Dallas, and Stanford University created a transistor with a working 1nm gate from carbon nanotubes and molybdenum disulfide (MoS2). "The semiconductor industry has long assumed that any gate below 5 nanometers wouldn't work, so anything below that was not even considered," said fir... » read more