Ubiquitous Trend In Design for Power (DFP) For IP And SoCs


Semiconductor design engineers must meet power specification thresholds, or power budgets, that are dictated by the electronic system vendors to whom they sell their products. Analyzing and reducing power across the board in all market segments has become a key requirement and a differentiator, especially over last 8 to 10 years for IP and IP-based SoC designers. Many products live and die due ... » read more

RTL Design-for-Power (DFP) Methodology


Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level tools are utilized as both design and verification tools, meaning that they help designers analyzing power and serve as the final ‘sign-off’ to ensure that power specifications are met. For standa... » read more

RTL Design-for-Power In Mobile SoCs


If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz. Mobile system-on-chips (SoCs) continue to clock faster and pack more functionality, yet are required to consume lower power for battery life and thermal considerations. Power consumption is a k... » read more

RTL Design-for-Power Methodology


This paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power. To download this white paper, click here. » read more

Watching And Waiting For DFP


By Ann Steffora Mutschler Although the semiconductor industry has been talking about the need to optimize SoC designs for power for many years, it is safe to say it’s still in the very early stages of the 'Design for Power' approach. That’s not to say that methodologies and tools are not in place. There are actually a number of options available, depending on the level of abstractio... » read more

RTL Design-For-Power Methodology


This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To download this white paper, click here. » read more

RTL Design-for-Power Methodology


This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To view this white paper, click here. » read more

Design For Power


By Ed Sperling Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different. While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality,... » read more