Synopsys sues Ubiquiti; multi-core parallel simulator; FPGA-based prototyping; display VIP; Mentor’s results.
Synopsys filed suit against Ubiquiti Networks and its project leader for “circumventing technological measures that effectively control access to Synopsys’ software.” The suit, filed in U.S. District Court in San Jose, claims that Ubiquiti used counterfeit keys obtained or created with tools from hacker websites to circumvent Synopsys’ License Key system. Ubiquiti, based in San Jose, develops wireless communication devices.
Cadence launched a new simulator based on multi-core parallel computing technology. According to the company, it improves performance over the previous generation by 3X for RTL design simulation, 5X for GLS, and 10X for DFT simulations. The simulator’s compile/elaboration process analyzes each design’s dependency graph and automatically maps it to the optimal number of cores to maximize speed.
Cadence also released a new FPGA-based prototyping platform, Protium S1. The platform is based on Xilinx Virtex-Ultrascale FPGAs and provides front-end congruency with the company’s Palladium Z1 emulation platform.
Aldec unveiled its latest HES prototyping board, HES-US-440, targeted at physical prototyping of small to medium sized ASIC designs up to 26 million gates and large FPGA designs. The company also released a new version of its HES-DVM software that enables simulation acceleration and emulation modes for the board in addition to physical prototyping.
Pro Design uncorked its proFPGA quad SG 280 modular and scalable high-speed FPGA prototyping solution. The system is assembled with four pluggable Intel Stratix 10 SG280-based FPGA modules and has a capacity of up to 80 million ASIC gates and up to 5 proFPGA quad systems with overall 20 FPGA modules that can be connected to increase capacity up to 300 million ASIC gates.
Avery Design Systems expanded its display VIP portfolio, adding support for HDMI 2.0b, DisplayPort 1.4, Embedded DisplayPort (eDP) 1.4b, DSI-2, and DSC 1.2. The VIPs support verification of both transmitter/source and receiver/sink and PHY designs as well as automated dynamic video and audio traffic generation and PHY bit rate clock generation.
Arteris won a deal with Dream Chip Technologies, which used Arteris’ interconnect IP and functional safety package in the design of an automotive ADAS development platform.
Spreadtrum chose Synopsys’ ZeBu Server-3 as its emulation solution for advanced mobile SoCs. Spreadtrum noted 40-minute Android boot and 5 MHz emulation performance.
Digital Media Professionals adopted Cadence’s Palladium XP Verification Computing Platform and Hosted Design Solutions to expand its emulation capacity and manage verification cycles remotely.
NetSpeed Systems’ interconnect IP portfolio was certified for the ISO 26262 automotive functional safety standard by SGS-TÜV Saar GmbH.
New statistical moment-based extensions for Liberty Variation Format (LVF) were ratified by the Liberty Technical Advisory Board. The new extensions provide a more precise static timing model based on non-Gaussian variation observed in designs operating at near sub-threshold voltage conditions. Applications include mobile and IoT IC designs.
Mentor Graphics released fourth quarter financial results with revenue of $478 million, up 41.7% from the fourth quarter last year. GAAP earnings per share for Q4 2017 were $1.05, up 106% from $0.51 in Q4 2016, while non-GAAP earnings per share were $1.21, up 92% from $0.63 in the same quarter last year. For the full fiscal year, revenues were $1.282 billion, up 8.6% from the year before. GAAP earnings per share were $1.37 for the year, up 69% from $0.81 in 2016 and non-GAAP earnings per share were $1.92, up 24% from $1.55. Mentor president Gregory K. Hinckley noted that fourth quarter bookings were up 40%, driven by scalable verification, integrated system design and new and emerging product categories. The acquisition by Siemens is on track, with 99.8% of votes approving in a special meeting of shareholders.