How shapes can affect the fin shape and BEOL capacitance in a finFET device.
Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have been used to successfully increase semiconductor device density, circumventing prior physical limits in pattern density. However, the number of processing steps needed in these patterning schemes can make it difficult to directly translate a lithographic mask pattern to a final product. Unfortunately, it is not straightforward to understand how a given photoresist shape will affect finished patterns on a chip. Small changes in the photoresist shape can unexpectedly modify the final pattern on chip, due to the complexity of subsequent process steps following photolithography.
Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of semiconductor fabrication processes. Virtual fabrication allows engineers to test semiconductor process changes and process variability in minutes or hours, instead of the weeks or months required to test their designs using actual semiconductor wafers. SEMulator3D is a virtual fabrication solution that can model process variability under complex patterning schemes and process flows.
SEMulator3D can be used to model the impact of variability in photoresist shape on the final patterns produced in a semiconductor device. In this study, we used SEMulator3D to model how photoresist shape affects the fin shape and back-end-of-line (BEOL) capacitance in a FinFET device. Variations in final patterns obtained using a self-aligned multi-patterning scheme were predicted, under conditions of sidewall profile variability in the starting photoresist shape.
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