Experts at the table, part 3: Challenges for multi-beam, direct-write, EUV, DSA and nano-imprint; how the market will shake out at 5nm and 3nm.
Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. (To view part one, click here. Part two is here.)
SE: Let’s talk about e-beam or direct-write lithography. For years, several vendors have been selling single-beam e-beam tools for direct-write lithography applications, mostly for niche-oriented markets. At the same time, the industry has been developing multi-beam e-beam tools for direct-write lithography, which are geared for mainstream IC production. But after years of R&D, multi-beam tools for direct-write are still taking root. What are the challenges?
Fujimura: On the direct-write side, the issue is still speed. You have to keep up with how many features you have to write on the wafer. If someone can solve the throughput problems with direct-write, it would be great. No question about that.
McIntyre: There are some technical and funding issues here. First, electrons don’t like each other as much as photons do. In direct-write, the electrons heat up the wafers. The throughput requirements are somewhere around 2,000 terabits per second to get 100 wafers an hour. That’s a lot of data. It’s also momentum. It’s very hard to build an industry solution when there are only one or two players that have a tool and are really exploring it. You’ve seen all that it’s taken for EUV to get to where it is today. That type of momentum, money and focus is really needed to overcome the physical challenges and the fundamental problems. There are a lot of issues to be addressed with direct-write. It takes time and money.
Levinson: There has always been the conceptual advantage of direct-write. That’s why people have been interested in it. There are just a lot of issues with it. The write times are usually related to the number of pixels you have. Every time you go to the next node, you now have twice as many of these pixels to write. You probably need more current because of the shot noise problems. The challenges grow much more quickly with e-beam node to node than they do on the optical side.
SE: On the other hand, multi-beam is making progress on the mask side of the equation. Two suppliers, Intel/IMS and NuFlare, are separately developing multi-beam tools for photomask production. That is a promising technology, right?
Fujimura: On the mask side, the eBeam Initiative recently conducted a survey. In the survey, industry luminaries believe that multi-beam mask writing is going to be real in the next few years. Some people say this year. Some people say next year. Most people, around 80%, say it will be in high-volume production use by 2018. It’s significant to have something that new to gain that kind of confidence. It will also take some time to make these tools suitable for high-volume production. But they seem to be on track.
Hayashi: The write times for each mask and the mask-set are increasing. Customers need a faster mask turnaround time. So, we need a faster writing system like multi-beam e-beam mask writers.
SE: Multi-beam mask writers appear to be for real. Can you use that technology to develop a system for use in direct-write lithography applications?
Levinson: If you think about this, the wafer stepper itself was an outgrowth of a mask patterning tool. It could be that once the technology gets used for making masks, maybe people can start to see ways to enhance it. In any case, the ability to make masks is a major step forward for multi-beam technology. It’s just a matter of seeing how successful the technology is. But now, we need to look and see what happens with these masks writers. Then, we can reassess it after we have some experience with them.
SE: Let’s move to nanoimprint lithography. Today, nanoimprint is being used in several non-IC applications. What about nanoimprint for chip manufacturing? Where is nanoimprint today and what are the apps?
Hayashi: The four-way cluster tools from Canon are in the process of being shipped. Currently, nanoimprint is focusing on NAND flash. The next target is DRAM. But first, we need to establish certain results with NAND flash. The current target is 1xnm NAND flash.
SE: What are the challenges?
Hayashi: The overlay for NAND flash is a little relaxed, compared with DRAM. So, the overlay has already reached a certain level. For defectivity, we still need an improvement of about two digits. In the last three or four years, we improved this by six digits. Of course, the defect target size is smaller. But we are still trying to reduce the defect density by some two digits in the next two years.
Levinson: Hayashi-san points out the defectivity problems for memory. It’s much more challenging for a logic maker. There is a two order magnitude problem for memory. It’s even bigger for logic. Again, if progress is made for the memory people, and there is some success there, we can go back and look at nanoimprint to see if more advancement might be possible. We will just wait now and see if at least the memory goals can be met before trying it for more ambitious goals in logic.
SE: What else?
Hayashi: We are trying to make a template for nanoimprint lithography. It’s at a 1X scale. With the current VSB e-beam systems, it requires a huge number of shots. The write times are long. So, we need a very small beam size. We also need a multiple beam system to get 1X features with good resolution and throughput. Fortunately, for the template, the writing size is quite small. One field is 26 x 33. It’s one-sixteenth that of a 4X reticle. But still, it could take five hours.
SE: Besides the traditional lithographic techniques, there is an emerging patterning technology called selective deposition. Using novel chemistries and tools, this technology can selectivity deposit materials on a surface. Is that making any progress?
Mitra: It’s still in the pathfinding stage. Again, that depends on what you call selective deposition. Just for the patterning aspect for selective deposition, you can say it’s still in R&D. Besides patterning, there are other areas where you can use selective deposition today. In the future, you may have 5nm and 3nm devices, and all different device architectures, using it. And there are many ways to do selective deposition. For example, there are several ways of developing a pattern from the ground up. These are further out in the roadmap.
SE: Finally, let’s make some predictions. We know 193nm immersion and multi-patterning will be used at 10nm. What lithography technology will prevail at 7nm, 5nm and perhaps beyond? Do you also have any predictions for memory or photomasks?
Levinson: As pointed out earlier, there is a little bit of danger tagging things to a node designation. Certainly, in two or three years, EUV will have reached a point that we are going to be able to apply it selectively to some layers. We’ll start to see it on a limited basis in manufacturing. And based on that, we will go forward to the next step, which is to expand its usage. Perhaps it will be used for more cut layers. Maybe we will get improvements in the mask blanks. Then, we can just pattern the metal layers directly. And then, if nothing else, one can fall back on EUV and double patterning. Obviously, there are a lot of challenges to do that. So whether EUV and double patterning is the solution, it’s unclear right now. But I will say we can continue to scale. There is an option. That’s one of them. It could be made to work. We’ll just have to decide if that’s the best one or we can do something else. But I can see a future in chip scaling for some time, if we solve several things. For example, there are the electrical conductivity problems or making a transistor that works.
Mitra: On the logic side, multi-patterning will probably be the main workhorse for a while. EUV will come in two to three years. And on the memory side, EUV could come in. In memory, if you only need one or two layers, it’s unclear if people will invest in the EUV infrastructure or not. Memory could also have some other options like DSA or nanoimprint. It really depends on cost.
McIntyre: So if what you call 7nm is the thing that is going to be ramping up by the end of 2017, that’s less than two years out. To have EUV as a front-up solution in that short time period is risky. So, we will most likely have an immersion-based solution. Or you can have immersion, and then you can back-insert EUV for cost savings over time. The next node could be two years after that. In order to scale to those types of dimensions, EUV is going to be a must. There will be a lot of EUV in that node. Even in that node and certainly in the following node, call it N3, you’ll see multi-patterning and EUV. So for N7, N5 and N3, EUV is certainly the front-up approach at this time. But there’s clearly room for a potential cost savings for insertion at particular levels for technologies like DSA and nanoimprint.
Hayashi: In some memory devices, nanoimprint technology will help for scaling. In the logic device area, without EUV, it’s quite difficult to continue scaling, especially if you want 5nm.
Fujimura: DSA, EUV, and, of course, multi-patterning will be used. Some of those technologies will have limited use in the next six years. On the mask side, meanwhile, there will be a transition in the e-beam world from VSB to multi-beam technology. That will be an interesting transition. VSB won’t go away. Some masks will continue to use VSB. Other things will require multi-beam.
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