Testability Analysis Based On Ever-Evolving Technology
By Pawini Mahajan - 06 Dec, 2022 - Comments: 0

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by high gate counts and an array of internally developed and third-party IP integrated into their designs. Understanding if one can create high-quality manufacturing tests for these complex designs mus... » read more

Ensuring Your Semiconductor Test Equipment Is Protected From Rising Cybersecurity Threats
By Eli Roth - 06 Dec, 2022 - Comments: 0

Cybersecurity threats pose risks to your business every day and can attack every aspect of your operation, and these threats are only increasing. According to IBM Security’s Cost of a Data Breach Report, in 2021, the average total cost of a data breach increased by nearly 10% year over year, from $3.86M to $4.24M – the largest single year cost increase in the last seven years. Sourc... » read more

Adding Differentiating Value And Reducing IP Integration Time for Your SoC
By Synopsys - 06 Dec, 2022 - Comments: 0

In the most efficient SoC design processes, semiconductor companies design their own, differentiated IP blocks, acquire high-quality third-party IP, configure it in an SoC-optimized way, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation ... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures
By Zhenhua Chen - 06 Dec, 2022 - Comments: 0

This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

Packetized Scan Test
By Siemens EDA - 06 Dec, 2022 - Comments: 0

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort. The Siemens solution for packetized deli... » read more

Why Matter 1.0 Really Matters
By Ed Sperling - 05 Dec, 2022 - Comments: 0

Incompatibilities of consumer devices inside the home are frustrating for consumers and a security risk. Skip Ashton, distinguished engineer at Infineon, talks about how the Matter 1.0 standard will fuse together different ecosystems from companies such as Apple, Google, and Amazon, how it will be applied to existing devices, what’s included and missing from the standard today, and how it can... » read more

Chip Industry’s Technical Paper Roundup: Dec. 5
By Linda Christensen - 05 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=67 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for u... » read more

Industry Adoption Of Line-Rate Network Security Using MACsec
By Maxim Demchenko - 05 Dec, 2022 - Comments: 0

Network security protocols are the primary means of securing data in motion — that is, data communicated between closely connected physical devices, or between devices, and even virtual machines connected using a complex infrastructure. This article will explore Media Access Control security (MACsec) and how it can be used to provide foundational level network security for a wide range of app... » read more

Research Bits: Dec. 5
By Jesse Allen - 05 Dec, 2022 - Comments: 0

Protonic programmable resistors for AI Researchers from the Massachusetts Institute of Technology (MIT) developed an analog deep learning processor based on protonic programmable resistors arranged in an array. In the processor, increasing and decreasing the electrical conductance of protonic resistors enables analog machine learning. The conductance is controlled by the movement of protons... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 02 Dec, 2022 - Comments: 0

With the European Council’s adoption of its negotiating mandate for the European Chips Act, member states and the Czech Presidency of the Council have reached a critical milestone in supporting Europe’s efforts to advance manufacturing and supply of critical components, while bolstering R&D capacities for development of next-generation semiconductor innovations, according to SEMI. Ch... » read more

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