What’s Next For Transistors And Chiplets


Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

High Thermal Die-Attach Paste Development For Analog Devices


Authors: Kiichiro Higaki, Toru Takahashi, Akinori Ono from Assembly Engineering Department Amkor Technology Japan, Inc. Keiichi Kusaka, Takayuki Nishi, Takeshi Mori from Information & Telecommunication Materials Research Laboratory, Sumitomo Bakelite Company, Limited Daisuke Koike, Masahiko Hori from Package Solution Technology Development Department, Electronic Devices & Storage Res... » read more

Blog Review: Oct. 20


Siemens EDA's Sumit Vishwakarma promotes ironing out preliminary bugs by using a real number model to describe an analog block as a discrete floating-point model and enable it to simulate in a digital solver at near-digital simulation speeds. Synopsys' Taylor Armerding explains how including security in the software development process from the beginning planning stages onward will help IoT ... » read more

Improving Accuracy In Satellite Navigation Systems


Increasing dependency on the global navigation satellite system (GNSS) constellations is raising concerns about what happens when signals are unavailable, even for short periods of time. GNSS systems affect our daily lives in ways we often don’t see, from location services to cell phone timing. In fact, these satellites have become a necessary part of critical infrastructure, and higher ac... » read more

Reaching silicon-based NEMS performances with 3D printed nanomechanical resonators


Abstract: "The extreme miniaturization in NEMS resonators offers the possibility to reach an unprecedented resolution in high-performance mass sensing. These very low limits of detection are related to the combination of two factors: a small resonator mass and a high quality factor. The main drawback of NEMS is represented by the highly complex, multi-steps, and expensive fabrication process... » read more

Effect Of Environmental Factors On ADAS Sensor Performance (AAA)


Abstract "Advanced driver assistance systems (ADAS) are becoming increasingly integrated within new vehicles sold in the United States. However, the majority of publicly available performance evaluations occur within idealized operation conditions in terms of weather, time of day, and sensor status, which are typically unrepresentative of naturalistic environments.  To evaluate the performa... » read more

Total Critical Area For Optimizing Test Patterns


Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in th... » read more

Manufacturing Bits: Oct. 19


Solar mini-reactors The University of Amsterdam has developed a standalone solar-powered mini-reactor. The technology could one day serve as an autonomous off-grid photochemistry system for remote locations. The prototype solar reactor measures 0.25 square meters. The system is equipped with a solar cell, which provides the power for the pumps and control system. This solar cell is placed ... » read more

Deep Dive Into Hardware Security Verification At This Year’s Osmosis User Group


We’ve been talking for months about how to successfully verify designs to avoid security weaknesses and vulnerabilities. In the upcoming Osmosis (OneSpin Meeting on Solution, Innovation & Strategy) user group event, attendees will get to hear first-hand from one of our most ardent users how they were able to secure their hardware design. The two-day, virtual event on November 3rd and 4... » read more

Power/Performance Bits: Oct. 19


Post-quantum crypto chip Researchers at the Technical University of Munich (TUM) designed and had fabricated an ASIC to run new encryption algorithms that can stand up to quantum computing. “Ours is the first chip for post-quantum cryptography to be based entirely on a hardware/software co-design approach,” said Georg Sigl, Professor of Security in Information Technology at TUM. “As a... » read more

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