Using Less Helium In Semiconductor Manufacturing

By Terry Powell - 22 Jul, 2021 - Comments: 0

Helium gas is increasingly in short supply. While consumers may be most familiar with it for use in filling balloons, it is used much more heavily in a variety of industrial processes – including semiconductor fabrication. As a result of supply concerns, many companies, including Lam, are looking for ways to reduce their helium usage. The making of a semiconductor chip involv... » read more

Eco-Friendly Initiatives For Semiconductor Sustainability

By Jessica Albright - 22 Jul, 2021 - Comments: 0

Global warming is a hot topic lately, pun intended, contributing to an over 2-degree temperature increase in the last two centuries—which might not seem significant until you factor in the larger stress it puts on our ecosystem (and economy): fire threats, water shortages, and increases in natural disasters. In the last four decades, damages from climate disasters have cost the US 2 trillion... » read more

Piecing Together Chiplets

By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Underlayer Optimization Method For EUV Lithography

By Brewer Science - 21 Jul, 2021 - Comments: 0

Photoresist and underlayer combine to serve a central role in EUVL for patterning. Layers will be very thin in future, because high numerical aperture (NA) and tight pitches will require very thin layers in the lithography stack. This thinness will make chemical interactions at the photoresist-underlayer interface more common. Adhesion between these layers will be critical to overcome pattern c... » read more

Survey: 2020 eBeam Initiative Annual Survey Results

By eBeam Initiative - 21 Jul, 2021 - Comments: 0

Aki Fujimura, the CEO of D2S, Inc. presented "The eBeam Initiative's Annual Survey Results at Photomask" at Photomask Japan 2021 in April 2021. Survey says that COVID has a net neutral business impact on total mask revenues. By 2021, 24% positive vs 20% negative COVID-related business predictions. 74% agree actinic inspection for EUV HVM by 2023, and more results. Click here to read more. » read more

Blog Review: July 21

By Jesse Allen - 21 Jul, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

Will An Adhesion Promoter Prevent Delamination In Power Semiconductor Packages?

By Amkor - 21 Jul, 2021 - Comments: 0

Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid electric vehicles (HEV) in the automotive market, demands on (and for) power packages have been growing. Packages for automotive applications must pass extensive testing for safety, therefore, packaging reliability is essential. As more semiconductor pack... » read more

New Power, Performance Options At The Edge

By Heidi Elliott - 21 Jul, 2021 - Comments: 0

Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

Innovative Dual Mark Design For Alignment Verification And Process Monitoring In Advanced Lithography

By UMC - 21 Jul, 2021 - Comments: 0

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafer. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this p... » read more

The Effects Of Poly Corner Etch Residue On Advanced FinFET Device Performance

By Coventor - 21 Jul, 2021 - Comments: 0

In this paper, we study the effect of poly corner residue during a 5nm FinFET poly etch process using virtual fabrication. A systemic investigation was performed to understand the impact of poly corner residue on hard failure modes and device performance. Our results indicate that larger width and height residues can lead to a hard failure by creating a short between the source/drain epitaxy an... » read more

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