Confusion Grows Over Packaging And Scaling
By Ann Mutschler - 15 Oct, 2020 - Comments: 0

The push toward both multi-chip packaging and continued scaling of digital logic is creating confusion about how to classify designs, what design tools work best, and how to best improve productivity and meet design objectives. While the goals of design teams remains the same — better performance, lower power, lower cost — the choices often involve tradeoffs between design budgets and ho... » read more

SystemVerilog Constraints
By Mentor, a Siemens Business - 14 Oct, 2020 - Comments: 0

This paper looks at two of the most common issues when constraint solver results do not match your intent: Not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra and not understanding the affect probability has on choosing solution values. Coding recommendations for improving your code to get better results are provided. To read more, click here. » read more

Maximizing Ansys LS-DYNA Performance With AMD EPYC 7Fx2 Processors
By Ansys - 14 Oct, 2020 - Comments: 0

AMD EPYC 7Fx2 processors bring high frequencies and very highs ratios of cache per core to the 2nd Gen EPYC family of processors. EPYC 7Fx2 processors build on the large memory capacity, extreme memory bandwidth and massive I/O of the 2nd Gen EPYC family to deliver exceptional HPC workload performance. This paper describes the excellent performance of these chips in running Ansys LS-DYNA comput... » read more

Why Data Format Slows Chip Manufacturing Progress
By SE Staff - 14 Oct, 2020 - Comments: 0

The Standard Test Data Format (STDF), a workhorse data format used to pull test results data from automated test equipment, is running out of steam after 35 years. It is unable to keep up with the explosive increase in data generated by more sensors in various semiconductor manufacturing processes. First developed in 1985 by Teradyne, STDF is a binary format that is translated into ASCII or ... » read more

IP Security Assurance Standard
By Accellera - 14 Oct, 2020 - Comments: 0

This whitepaper is available from the IP Security Assurance (IPSA) Working Group that describes Accellera’s initial proposal to address the industry’s security concerns involving IP integration. Since integrators typically treat IP as a “black box,” vulnerabilities may inadvertently be inserted into an SoC/ASIC. The whitepaper details the objectives of the IPSA standard and its approach... » read more

13-Gb/s Transmitter For Bunch Of Wires Chip-To-Chip Interface Standard
By Fraunhofer IIS/EAS - 14 Oct, 2020 - Comments: 0

Continuous downscaling of integrated circuits has reached a bottleneck. Technologies such as system in a package, multi-chip module and integration of chips on an active or passive interposer can further improve the system performance. Bunch of wires interface standard was recently introduced for chip to chip short interfaces within a package. This standard required both terminated and untermin... » read more

Blog Review: Oct. 14
By Jesse Allen - 14 Oct, 2020 - Comments: 0

Arm's Hongsup Shin explains a machine learning application that can determine which tests are most likely to find hardware bugs, improving efficiency and reducing the number of tests that need to be run. Synopsys' Pieter van der Wolf and Dmitry Zakharov take a look at the increasing need for low power processors optimized for machine learning tasks as IoT, smart home, and wearable devices pr... » read more

Security Verification of Rambus’ CryptoManager Root of Trust by Tortuga Logic
By Rambus - 14 Oct, 2020 - Comments: 0

The confidentiality and integrity of cryptographic key material is critical to maintaining system security. A hardware root of trust, such as the Rambus CryptoManager Root of Trust, is designed to securely generate, store, and employ cryptographic keys. Tortuga Logic has independently verified the policies surrounding access to keys stored within registers in the CryptoManager Root of Trust usi... » read more

Reliability Over Time And Space
By Ed Sperling - 13 Oct, 2020 - Comments: 0

The demand for known good die is well understood as multi-chip packages are used in safety-critical and mission-critical applications, but that alone isn't sufficient. As chips are swapped in and out of packages to customize them for specific applications, it will be the entire module that needs to be verified, simulated and tested, and analyzed. This is more complicated than it sounds for s... » read more

Demand Grows For Reducing PCB Defects
By Anne Meixner - 13 Oct, 2020 - Comments: 0

Board manufacturers are boosting their investment in inspection, test and analytics to meet the increasingly stringent demands for reliability in safety-critical sectors like automotive. This represents a significant shift from the past, where concerns about reliability primarily targeted the devices connected to printed circuit boards. But as SoCs become disaggregated into advanced packages... » read more

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