From Design To Deployment: How Silicon Lifecycle Management Optimizes The Entire IC Life Span
By Steve Pateras - 13 Oct, 2020 - Comments: 0

The beginning of the IC journey gets most of the attention in the semiconductor world – the challenges of design, test and manufacturing. But the reality is the entire lifecycle of a chip needs attention, requiring ways to ensure a chip’s intended and ongoing operation, especially in ever-changing operating environments where chips ultimately reside. The growing complexity of today’s e... » read more

Scramble For The White Space
By Bryon Moyer - 13 Oct, 2020 - Comments: 0

Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

Eliminating Ground-Loop Induced Noise
By Peter Andrews - 13 Oct, 2020 - Comments: 0

As semiconductor device performance increases, especially for low power and higher speed ICs, testing low frequency 1/f, RTN and phase noise with improved signal-to-noise ratio is required. Finding and eliminating unwanted noise is required in multiple areas. Noise sources can be found inside a prober, outside a prober, and in a measurement TestCell. Historically, TestCell-generated noise was o... » read more

Key Aspects Of Yield Management Systems For Fabless Startups
By Marie Ryan - 13 Oct, 2020 - Comments: 0

Do you work for a fabless start-up? Are you ramping up? If so, you need data-analysis tools for your production data. You will struggle without them. You have two options for yield management analysis. You may decide to hire an engineer (or team of engineers) whose job is to transfer the data from datalogs to a spreadsheet, then generate reports. Or, you could invest in a system that takes c... » read more

Ambiq YieldHUB Case Study
By yieldHUB - 13 Oct, 2020 - Comments: 0

Ambiq Micro is leading the world in energy-efficient micro-controller (MCU) design, redefining "ultra-low-power" with its unique and proprietary SPOT platform. They began working with us a few years ago when their data started scaling (they now produce thousands of wafers a month!) and they needed an effective yield management system to help them. Senior Product Engineer Jerry Kao shares his fa... » read more

The Quest To Make 5G Systems Reliable
By Ed Sperling - 13 Oct, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss 5G reliability with Anthony Lord, director of RF product marketing at FormFactor; Noam Brousard, system vice president at proteanTecs; Andre van de Geijn, business development manager at yieldHUB; and David Hall, head of semiconductor marketing at National Instruments. What follows are excerpts of that conversation. SE: How do we measure the reli... » read more

Manufacturing Bits: Oct. 12
By Mark LaPedus - 12 Oct, 2020 - Comments: 1

MoSi2 pellicles for EUV Hanyang University has presented a paper that describes a novel molybdenum disilicide (MoSi2) pellicle membrane for use in extreme ultraviolet (EUV) lithography. With a 28nm thickness, a MoSi2 membrane has demonstrated a 89.33% transmittance for EUV lithography. The pellicle technology is still in R&D. MoSi2, which is a silicide of molybdenum, is a refractory cer... » read more

What’s WAT? An Overview Of WAT/PCM Data
By yieldHUB - 12 Oct, 2020 - Comments: 0

Wafer acceptance testing (WAT) also known as process control monitoring (PCM) data is data generated by the fab at the end of manufacturing and generally made available to the fabless customer for every wafer. The data will typically have between forty and one hundred tests, each test having a result for each site (or “drop-in”) on the wafer. The sites are located so that the fab can monito... » read more

Resolving Particle Issues In Photolithographic Scanners
By CyberOptics - 12 Oct, 2020 - Comments: 0

Case Study: It’s essential to quickly identify the source of airborne particles in photolithographic scanners — both to coordinate and confirm the effects of cleanings and repairs. Regrettably, most traditional methods for detecting particles have trouble addressing particle issues proactively. Consider in-situ methods as an example. Conventional in-situ scanners do not provide access to... » read more

New Test Methods For 5G Wafer High-Volume Production
By FormFactor - 12 Oct, 2020 - Comments: 0

In order to provide the chips required for this change in the landscape, there will be a large number of changing requirements in wafer test that come out of these architectural requirements. Form Factor partnered with Intel to investigate these changes, and tested one such example of a new test methodology. In a joint collaboration with Intel to develop a test methodology for their 5G RF-So... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy