FinFET Reliability Issues


The 16nm FinFET node has introduced several new challenges in the IC design community. In addition to the complexity of power-noise and electromigration (EM) verification, thermal reliability has become a major concern for both chip and package designers. With the three-dimensional architecture of FinFET devices, new simulation approaches are being used to model thermal behavior of the die in o... » read more

Do We Need A “Glue” Engineer?


Design and verification are so complex today and fraught with market risk that it keeps managers awake and sweating at night. So much of design is carved up in IP blocks and subsystems, each with their own verification issues and methodologies. To manage the complexity the design is partitioned, and so too are the teams. But as software verification becomes more crucial to system-design succ... » read more

Automation Can’t Replace Human Intervention


We work in a dynamic industry where the focus is on making it easier to design and verify semiconductor chips by automating tasks for the design engineer. There is so much emphasis on this that I wonder if it is easy to forget the value of that designer’s experience. No matter how automated a process gets, there is always the fundamental assumption that the engineer knows what is happening be... » read more

The Power-Performance Paradox


The Changing World Technology is shaping and altering the world around us. Reality is being augmented and “virtual reality” is becoming the norm. Video is becoming more immersive, offering 3D effects and 4K resolution, with 8K on the horizon. Cars are a technology showcase that in a few years conceivably will take over the driving for us. Our ability to interact with technology through tou... » read more

UPF-Friendly RTL


On a recent customer visit, we were introduced to a new term – new to us at least – “UPF-friendly RTL”. While I hadn’t heard the term, I have been going on about the concept for some time – to the point, no doubt, of becoming terminally boring. We’ve had several customers quietly doing this for years, but now I’m starting to hear it from more customers, and from 1801 committee m... » read more

Power Grid Simulation


Introduction The underlying solver algorithms used in power grid (PG) simulation today are derivations of circuit simulation algorithms first developed many decades ago. In fact, the 40th anniversary of SPICE (a widely used circuit simulator), was celebrated in 2011. As such, it is understandable that many engineers have a jaundiced view towards claims of improved PG simulation performance. Ne... » read more

28nm Powers TSMC Forward (Part Deux)


TSMC’s financial results for the 4th Quarter of 2013 and for the full year were announced just a few weeks ago, with TSMC stating it had again achieved record sales and profits. TSMC continues to own the 28nm foundry market. TSMC a year ago stated plans to have 20nm as its next technology node in production in 2014 and it looks to be delivering on this projected claim with the announcement th... » read more

With Low-Power Comes Great Responsibility


Recent trends in the consumer electronics market show a demand for short, slim, and light-weight but powerful devices (with the only exception being displays, which are getting larger). Therefore area, timing, and power have all become “critical” to design; whereas in the past, one was prioritized over the others depending on design requirements. However, power is the dominant factor tod... » read more

Power Verification in Sochi?


An estimated 3 billion viewers watched in wonder at the high tech artistry of the opening ceremonies of the $50 billion Sochi Winter Olympics. As many viewers later learned, these events are often not without glitches. The after buzz was all about the Olympic ring failure. When only four of the five snowflakes transitioned into rings, the broadcasters resorted to rehearsal footage attempting to... » read more

Schedule Versus Specifications


With power being paramount in SoCs today, I was surprised to hear the amount of time spent on power reduction exercises can be only a few days. According to William Ruby at Ansys/Apache, how much time engineers spend on power reduction activities depends on how sensitive the design is to power and whether they are still trying to meet the power spec or -- based on the early power estimates �... » read more

← Older posts Newer posts →