category: Blogs – LPHP

category: Auto, Security & Edge AI

It’s Never Too Early
By David Hsu - 13 Feb, 2014 - Comments: 0

My previous postings discussed the importance of native low-power capabilities and coverage in simulation flows. The complement to this is incorporating complete and thorough low power checking throughout the design and implementation flow, and find and fix as many low-power bugs as possible before simulation. With the right checking tools and proper deployment, doing so enables the possibility... » read more

Stimuli-Driven Power Grid Analysis
By Marko Chew - 13 Feb, 2014 - Comments: 2

The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, logic simulation is used to generate the complete activity suite. Vector mode is typically referred as a VCD (Value Change Dump).... » read more

What Goes Around Comes Around: Moore’s Law At 10nm And Beyond
By Greg Yeric - 13 Feb, 2014 - Comments: 2

Modified by Greg Yeric from original by Eric Fischer Gordon Moore penned his famous observation in an era when the people developing the process were also the people designing the circuits. Over time, things got more complicated and work specialization set in, but all was well in the world for many years as the fabs kept delivering on Moore’s Law. Yes, designers had to come up with lot... » read more

Choosing The Right Systems Design Path
By Brian Fuller - 13 Feb, 2014 - Comments: 0

I’m a cheap bastard, usually given to self-abnegation when it comes to buying material goods for myself. But I broke down and bought a runner’s watch late last year because I wanted to change up my exercise routine to run the same distances, only faster. I quickly decided against going all in and getting a GPS watch. At this point in the arc of electronics-design technology, it’s hard ... » read more

The Other Side Of Formal
By Joseph Hupcey III - 13 Feb, 2014 - Comments: 1

It’s natural to think of formal analysis as a ruthlessly effective bug hunter and verification tool. But as the following case study from Homayoon Akhiani, presented at the Jasper Users Group (JUG) meeting shows, customers are using this approach to increase their SoC’s performance in ways that are very visible to the end-user of the part. Such visible improvements — in this case, minimiz... » read more

ESD Signoff No Longer A “Nice to Have” In FinFET Design Era
By Karthik Srinivasan - 13 Feb, 2014 - Comments: 0

As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts. Technology ... » read more

Making Waves In Low-Power Design
By Barry Pangrle - 16 Jan, 2014 - Comments: 0

Barry Pangrle In a blog last April we looked at a potential candidate technology that just might be able to produce an economically feasible method for implementing delay insensitive circuits in CMOS. The basic idea behind this technology has been around since at least the 1990s and is better known as Null Convention Logic™ (NCL). Much of the work in this area was pioneered by Karl Fant and ... » read more

Three Must-Watch Electronics Trends in 2014
By Brian Fuller - 16 Jan, 2014 - Comments: 0

It’s halfway through January, and I think we’ve exhausted our “2014 Forecast” posts for the year. Still, it’s helpful to consider what lies ahead when all we have under our belts at this point is CES 2014 (and that event was clearly underwhelming as a technology bellwether). I propose three areas to watch closely in 2014, based on ploughed ground from some excellent industry observ... » read more

Power Grid Analysis—Challenges At 20nm And Below
By Christen Decoin - 16 Jan, 2014 - Comments: 1

Introduction The need for power grid analysis (PGA) emerged in the early 2000s, when leading-edge semiconductor companies were starting 90nm designs that unveiled new technical challenges. Since then, PGA has coped with diverse challenges for each new technology node, including coverage (dynamic PGA emerged in the mid-2000s), performance, and capacity (a bottleneck at the 32/28nm node). But 20... » read more

Using USB 3.1’s Multiple INs To Reach 10 Gbps Data Rates
By Matthew Myers - 16 Jan, 2014 - Comments: 0

In January 2013, the USB-IF announced USB 3.1, a new generation of the protocol that will double USB 3.0 data throughput performance to 10 Gbps. In addition to this increased speed, the specification requires compatibility with existing cables, connectors, software stacks, and device class protocols. USB 3.1 products must support existing 5 Gbps and new 10 Gbps hubs and devices, as well as olde... » read more

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