category: Blogs – LPHP

category: Auto, Security & Edge AI

Verifying Power Optimized Designs Using Sequential Analysis
By Rob Eccles - 16 Jan, 2014 - Comments: 0

All power optimization tools can perform combinational optimization, where there is an opportunity to gate a register clock input, based on the combinational logic that is feeding the register’s data input. While this method works well and does not alter the logic behavior at the register, the problem is that it leaves additional power saving opportunities on the table. However, sequential... » read more

Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era
By Aveek Sarkar - 16 Jan, 2014 - Comments: 1

There is a greater focus on power noise and reliability simulations and sign-off as the complexity of SoC designs continue to increase with 100+ different voltage islands, clock and power gating techniques, and multiple IPs each operating on different clock and power domains, etc. The technology node migration from 40nm to 20nm is driving requirements for electro-migration (EM) and reliability ... » read more

Power Resolutions For 2014
By Mark Baker - 16 Jan, 2014 - Comments: 0

As the ball dropped at midnight in New York’s Time Square, signifying the beginning of 2014, many had already decided on their resolutions for the New Year. Others decide during the first few days of the New Year. Undoubtedly, consideration involves common resolutions that we fall back on year after year. Individuals might think about health, losing weight and becoming more fit. Others think ... » read more

Simple Does Not Mean Easy
By Ann Mutschler - 16 Jan, 2014 - Comments: 0

When it comes to chip design we speak constantly about managing complexity - how best to architect for it, how to manage it, what design techniques to use, what the impact on the system will be etc. - but we don't speak too much about making the design more simple. Instead, we heap on more complexity to manage the complexity. As with everything else in life it seems just because something is... » read more

Fastest Computers On The Planet
By Barry Pangrle - 05 Dec, 2013 - Comments: 0

The latest Green500 list (Excel spreadsheet here) was just released at the end of last month and heterogeneous systems now own the top of the list. The Top 10 systems all use a combination of Intel Xeon (mostly E5) processors paired with NVIDIA K20s. There are now 6 systems listed that have broken the 3,000 MFLOPS/W barrier and TSUBAME-KFC, belonging to the Tokyo Institute of Technology’s GSI... » read more

3D-IC Requires Expanded Power Grid Analysis
By Christen Decoin - 05 Dec, 2013 - Comments: 0

At advanced nodes, effective power grid analysis is critical to ensure that the small dimension interconnects can handle current demands without introducing potential failure modes or signal integrity issues. Existing software tools for power analysis need to be extended and enhanced for 2.5D and 3D designs to fulfill new requirements and use models. This article describes some of the needed im... » read more

How Reliable Are Interconnects In 16nm FinFET Designs?
By Arvind Vel - 05 Dec, 2013 - Comments: 0

The 16nm FinFET process node is rapidly becoming the preferred choice for advanced Integrated Circuit (IC) designs. The 16nm node’s lower standby leakage characteristics and increased drive strength capability enable IC designers to push the boundaries of low power – high performance designs. However, the choice of the node is also accompanied by reduced reliability margins, requiring desig... » read more

Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics
By David Hsu - 05 Dec, 2013 - Comments: 0

Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for verification tasks is crucial to achieving closure on overall goals, and creating the comprehensive set of metrics to track during the verification process enables schedule predictability and confi... » read more

Door Busters In Low Power Optimization
By Mark Baker - 05 Dec, 2013 - Comments: 1

The holiday season is upon us, notably a shortened gift buying season at that, which for some only adds to the anxiety felt at this time of year. Many shoppers are out there searching for a door buster deal on that “hot item,” but choices must be made on where to allocate one’s time. Should one stop with the door buster deals or take the time to look further for more practical or traditio... » read more

Power Optimization Considered
By Abhishek Ranjan - 05 Dec, 2013 - Comments: 0

The explosive emergence of hand-held computing and entertainment devices fuels an ever-increasing demand for longer battery life. In fact, 70% of all new hardware development is targeted toward mobile devices. Ancillary to this phenomenon, technology scaling has increased the number of transistors that can be packed per unit area. More and more functionality can be put into electronic devices. ... » read more

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