category: Blogs – LPHP

category: Auto, Security & Edge AI

Lightening The Information Overload
By Abhishek Ranjan - 22 Nov, 2013 - Comments: 0

We live in an age where it’s very easy to suffer from information overload — even when that information leads to better designs. Power optimization tools have been very well received in the market, with almost every major electronics company using these tools and seeing the benefits. Yet, if a power optimization tool shows you everything you can do to improve your design, it’s too much... » read more

User Case Study
By Joseph Hupcey III - 08 Nov, 2013 - Comments: 0

In prior articles I’ve written in general terms of about formally verifying the impact of adding low power control circuitry with Jasper’s Low Power Verification App. At the recent Jasper User’s Group meeting on Oct. 22, a real world case study of this app in action at STMicro’s R&D center in India was presented. Here are some highlights from this paper: DUT in question: an AR... » read more

What Do Timing Constraints Have To Do With Clock Domain Crossing?
By Ramesh Dewangan - 07 Nov, 2013 - Comments: 0

As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality timing constraints not only reduce the total effort required to achieve timing closure, but also reduce the number of iterations during that process. In the worst case, incorrect timing constraints ca... » read more

ARM Cortex-A53, UPF & FD-SOI
By Barry Pangrle - 07 Nov, 2013 - Comments: 0

The IEEE Standards Association Symposium on Electronic Design Automation (EDA) Interoperability was held on Oct. 24. I found the first session, Interoperability Challenges: Power Management in Silicon, with presentations by Erich Marschner of Mentor Graphics and Stuart Riches and Adnan Khan (both from ARM) to be particularly interesting. Earlier this year, the IEEE announced a new version of UP... » read more

Low-Power Crisis = Danger & Opportunity
By Brian Fuller - 07 Nov, 2013 - Comments: 0

If you’re a student of these things, you’ve no doubt heard that in Japanese, the word “crisis” is divided equally into “danger” and opportunity.” The biggest opportunity for electronics designers is also their biggest challenge: power management. Ask anyone today and they’ll tell you that minding and managing power consumption and leakage is a big concern. How big? At DAC... » read more

FinFET Impacts For Reducing Physical IP Power Consumption
By Navraj Nandra - 07 Nov, 2013 - Comments: 0

FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and process‐induced variability below 32-nanometer. FinFET technology is now in volume production. To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That include... » read more

Current Generation Of FPGAs Pose New Power And Reliability Challenges
By Annapoorna Krishnaswamy - 07 Nov, 2013 - Comments: 0

Today’s FPGAs are being used in a wide variety of applications such as consumer electronics, computer and storage, automotive electronics, and mission critical applications. The flexibility to configure the device based on its need, the ability to reprogram its functions, and the hardware parallelism it offers to quickly process very large amounts of data are some of the reasons why off-the-s... » read more

Don’t Stop Listening
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

While it has been some years now, I admit I used to be a dedicated Blackberry user and could not understand the fascination with the iPhone initially. I knew exactly how my Blackberry worked, I loved the keyboard (or so I thought) and while a Macophile as well, I was reluctant to switch to a new smartphone, even though it was from my favorite PC maker. And then I had a chance to play with an... » read more

Thermals And New Technology Nodes
By Barry Pangrle - 10 Oct, 2013 - Comments: 1

I recently had a friend in EDA ask me about how important thermal analysis is going to be with new FinFET technologies.  I told him that I honestly haven't had too much direct experience with 16nm FinFET yet, but in general, I'd expect thermal analysis to be somewhat more important as feature sizes shrink regardless of whether it's FinFET or planar. Part of my reasoning behind this is that sma... » read more

Reliability Challenges In 16nm FinFET Design
By Arvind Vel - 10 Oct, 2013 - Comments: 1

As the IC industry rapidly adopts the 16nm technology node, IC designers are faced with a new wave of reliability challenges. The 16nm node has introduced several changes in the way that the devices are fabricated and how the metal stack-up is built. On one hand designers gain speed, leakage and density improvements. On the other, reliability engineers need to address the narrowing electromigra... » read more

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