Low Power Verification – “X” Marks the Spot


Welcome to a new discussion on a range of topics we think will be interesting to folks who design and verify SoCs. Though the name of this blog denotes two top attributes of SoCs—IP implementation and the pervasive need for low power (LP), we certainly may go far beyond the scope of these topics in upcoming posts. We’ll start with a topic on the LP side, and going forward we’ll alternate ... » read more

Mobile Technology Unchained


Smart phones and tablets mandate that designers place equal, if not more, emphasis on optimizing power consumption. Everyone wants a fast device, high resolution graphics, and light weight, but they don’t want to be chained to their battery chargers. Reducing power consumption is high on everyone’s list. There are several different approaches to reduce power consumption and thereby produ... » read more

Embedded Memory Impact On Power Grids


Introduction Due to the overwhelming technical advantages of having on-chip memories, embedded memories are ubiquitous in most chip designs, and can comprise significant portions of a chip (upwards of 50%, according to some authors). Accordingly, a chip’s power grid design and analysis must account for the impact of these embedded memories, but design teams often struggle to resolve power... » read more

HotChips: Power8


It’s another year, another HotChips Conference and another update on IBM’s POWER processor. IBM continues to impress with its big iron processor, and this year it’s the new POWER8. IBM announced more details of its new POWER8 processor at HotChips and IBM now joins Intel at 22nm, but with the twist that IBM’s process is based on SOI technology. The POWER8 quadruples the thread count ... » read more

How Secure Are Low-Power Techniques?


As a chip designer, you and your team have done the best job possible to optimize power in your SoC, likely utilizing all of the low power techniques at your disposal. The chip tapes out, gets implemented into systems and it’s a success! Then the call comes that your chip has been hacked within the system it’s in and you and your team are left shaking your heads in wonder. I can imagine ... » read more

The IC Supply Chain: The Day After Tomorrow


Last month, I wrote about the implications of hacking in a connected world. Judgment Day from the Terminator franchise came to mind. All that paranoia is still “out there” a bit, I admit. Let’s bring it down to a more pedestrian level in this post… Plenty has been written about the disaggregated, distributed, worldwide semiconductor supply chain. Design groups all over the world work... » read more

Need For Unified Chip-Package Analysis


For anyone involved in the system-on-chip (SoC) design cycle over the past few years, it is easy to see that the functionality of the chip has become more diverse with the addition of new features and duplication of main functions to drive higher throughput. This trend coupled with the need to maintain low power through various techniques such as voltage islands and power and clock gating have ... » read more

Equivalence Checking


Everyone is consumed by power these days. The less power our devices use, the better—the longer our batteries will last, the more applications we can use simultaneously, the less HVAC capacity is required by the data center, etc. Clock-gating is one widely used technique to save power in ASIC designs. However, clock gating can significantly impact the structural and behavioral elements of the... » read more

Power Grid Analysis


By Christen Decoin With increasing design size at each technology node, power grid analysis (PGA) has been stretching established software capacity and performance for some time. At 32/28nm, capacity and performance issues finally presented significant barriers to achieving signoff. In this article, we explore existing approaches that EDA vendors have been trying to leverage to work around ... » read more

Why Does That App Make My Phone Hot?


By Adam Sherer Popular Mechanics examined this topic in 2011, focusing mostly on packaging and other physical conditions. “Poor signal, intense workload and battery charging” were quoted, but the verification engineer knows the part of that list that was glossed over—intense workload. The author of that article waved away that aspect, saying the operating system usually can handle the so... » read more

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