category: Blogs – LPHP

category: Auto, Security & Edge AI

Hierarchical LP Design 2
By Luke Lang - 11 Aug, 2011 - Comments: 0

By Luke Lang Last month, I discussed two key features of the Common Power Format (CPF) that support hierarchical design methodology: boundary port and macro model. These are commands that need to be written to describe the power intent and drive the tools. Without these commands, it is extremely difficult to do hierarchical design. But with these commands, hierarchical power intent files are n... » read more

Interconnect Power
By Barry Pangrle - 11 Aug, 2011 - Comments: 0

By Barry Pangrle Applied Materials announced its latest version of nano-porous low-k dielectric technology called Black Diamond 3 last month at Semicon West. What really caught my ear though was the marketing claim that 1/3 of total chip power consumption (really energy) is in the interconnect. I thought about this a bit, and certainly for some designs this seemed to easily be quite po... » read more

Don’t Forget Test
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

In the modeling of designs for power, engineers make sure to include real system modes and get real activity vectors but, according to Pete Hardee at Cadence, there are a few things they are forgetting. “If the only activity you are using is your simulation test vectors, those are probably pretty unrealistic and that’s a big source of error. One other thing we see—and this is quite imp... » read more

The Evil Doctor
By Atrenta - 28 Jul, 2011 - Comments: 0

I’ve always been a fan of superhero movies. I would say the Terminator series is the last time I really liked Arnold Schwarzenegger. I bet I’m not alone in that opinion. I think it’s terrific when downtrodden bands of X-Men use their strange powers to defeat evil. The summer blockbuster season is in full swing with movies like Green Lantern and Captain America. A good time will be had ... » read more

Top 5 Reasons For Power Consumption Waste
By William Ruby - 21 Jul, 2011 - Comments: 0

By William Ruby Low-power seems to be on everyone’s mind these days, and it’s not just the chip design teams. One common consumer complaint is that the “battery life is way too short”! And of course, we all know this one, “OMG – that laptop is sure hot“! Even data center facilities managers lament, “We can’t supply enough power to the equipment—and when we do, we can’t co... » read more

Hierarchical LP Design
By Luke Lang - 21 Jul, 2011 - Comments: 0

By Luke Lang The rapidly shrinking process geometry is a double-edged sword. It allows unprecedented integration of circuits. But it also produces leakier transistors, which is one of the main reasons behind the need for low-power design techniques. Therefore, a good low-power design flow must not only automate low-power design, verification, and implementation, it must also support hierarchic... » read more

Building A Better CMOS FET
By Barry Pangrle - 21 Jul, 2011 - Comments: 0

By Barry Pangrle SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice overview presentation on FinFETs. From a power and performance standpoint, we’ve seen some early pre-production information released from Intel that I briefly discussed here. Serge�... » read more

Aren’t We Beyond That?
By Ann Mutschler - 21 Jul, 2011 - Comments: 0

The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of late. According to Cadence’s Pete Hardee, even though the industry is spending a lot of time looking ahead to architectural-level power modeling and virtual prototyping, the need for detai... » read more

Low Power Simulation
By Luke Lang - 16 Jun, 2011 - Comments: 0

By Luke Lang Once in a while I’m asked if it’s necessary to check power and ground connections with VDD/VSS-aware simulation on a physical (PG) netlist. The short answer is: “No, as long as you have run LP structural verification. But if it will help you sleep better at night, then go for it.” For the longer answer, keep reading. In order to run VDD/VSS-aware simulation, one must ha... » read more

The Tough Metric: Energy-Efficiency
By Barry Pangrle - 16 Jun, 2011 - Comments: 0

By Barry Pangrle Jem Davies, fellow and vice president of technology at ARM, gave a keynote address on Computing Power and Energy-Efficiency Tuesday morning at the AMD Fusion Developer Summit in Bellevue, Washington. His scheduled appearance at the summit led to much speculation and rumor a while back, especially within the context of the ARM versus x86 battle for market share in the tablet ar... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy