Scaling AI Infrastructure: The Critical Role Of PCIe 7.0 Retimers


In a previous blog, Scaling in the AI Era: The Role of PCI Express 7.0 Switches in Next-Gen Data Centers, we explored how PCIe 7.0 switches enable high-bandwidth, low-latency interconnects for AI-driven data centers. Switches are essential for building flexible, composable architectures that connect thousands of GPUs, accelerators, and memory subsystems. But as AI clusters grow in size and comp... » read more

Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis


The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Predictable Design Optimization And Closure With Adaptive Scenario Compression


Modern semiconductor chip design faces growing complexity due to numerous timing scenarios driven by varying operating conditions and physical effects. This complexity is especially pronounced in mobile and automotive chips, which require optimization across diverse performance and reliability demands. Designers currently focus on a limited subset of scenarios to manage computational load, but ... » read more

Future Architecture Technologies: POE2 And vMTE


Future Architecture Technologies are features being developed for currently unreleased versions of the Arm architecture. Arm provides the ecosystem with relevant information and specifications in advance, ensuring software support for when new technologies are realized in hardware. This blog introduces two future technologies: Permission Overlay Extension version 2 (POE2), and Virtual T... » read more

PCIe Low-Power Validation Challenges And Potential Solutions


As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

The Future Of Digital Engineering In The Age Of AI


Digital engineering gives innovators creative agency to test the limits of their ideas in a virtual environment. It is in this convergence of digital technologies, data-driven models, and advanced simulations where new designs are born at unprecedented levels of speed and accuracy. Adding artificial intelligence (AI) into the mix further accelerates innovation by unlocking opportunities to a... » read more

Unlocking Clarity: Keyphrase Trees Bring Structure To AI Text Analysis


By Amr Hegazy, Mohamed Abdelkarim, and Reem El Adawi In the vast digital landscape of information, from intricate design specifications to extensive patent literature and complex verification reports, extracting meaningful insights often feels like searching for a needle in a haystack. This challenge is particularly acute in the semiconductor industry, where critical details are buried with... » read more

Advanced Packaging: A Key Technology For The Next Generation Of Electronics


In recent years, advanced packaging has become much more important. While semiconductor manufacturers used to focus primarily on miniaturization and increasing the performance of individual chips, the focus is increasingly shifting to the system level: How can processor cores, memory, sensors, and wireless modules be integrated as efficiently, compactly, and powerfully as possible within a sing... » read more

Integrated Modular Firmware Solutions: A Vital Component Of Custom Silicon Chiplet Architecture Designs


By Marc Meunier and Srini Narayana The shift from monolithic SoC designs to chiplet-based architecture isn’t just a packaging innovation. It’s a fundamental rethinking of how custom silicon is designed, manufactured, and deployed. This transition is driven by the growing impracticality of scaling large monolithic dies at advanced nodes. As die sizes increase, so do the costs, yield ri... » read more

Achieving Reliable 2m+ DAC Connectivity For AI Scale Networks With 224G PHY IP


As artificial intelligence workloads and hyperscale data centers continue to evolve, the requirements for networking infrastructure are becoming increasingly stringent. High-speed, reliable connectivity is essential to support the massive data flow and low-latency demands of AI-scale environments. Passive direct attach copper (DACs) remains an attractive choice for hyperscalers and system vendo... » read more

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